MSP430FR6889 Datasheet, PDF (9/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

www.ti.com
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
4.2 Pin Diagram – PN Package – MSP430FR688x, MSP430FR688x1
Figure 4-2 shows the 80-pin PN package pin assignments.
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
P1.4/UCB0CLK/UCA0STE/TA1.0/S3
P1.5/UCB0STE/UCA0CLK/TA0.0/S2
P1.6/UCB0SIMO/UCB0SDA/TA0.1/S1
P1.7/UCB0SOMI/UCB0SCL/TA0.2/S0
R33/LCDCAP
P6.0/R23
P6.1/R13/LCDREF
P6.2/COUT/R03
P6.3/COM0
P6.4/TB0.0/COM1/S36
P6.5/TB0.1/COM2/S35
P6.6/TB0.2/COM3/S34
P2.4/TB0.3/COM4/S33
P2.5/TB0.4/COM5/S32
P2.6/TB0.5/ESIC1OUT/COM6/S31
P2.7/TB0.6/ESIC2OUT/COM7/S30
P3.0/UCB1CLK/S29
P3.1/UCB1SIMO/UCB1SDA/S28
P3.2/UCB1SOMI/UCB1SCL/S27
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
ESIDVCC
P9.7/ESICI3/A15/C15
P9.6/ESICI2/A14/C14
P9.5/ESICI1/A13/C13
P9.4/ESICI0/A12/C12
P9.3/ESICH3/ESITEST3/A11/C11
P9.2/ESICH2/ESITEST2/A10/C10
P9.1/ESICH1/ESITEST1/A9/C9
P9.0/ESICH0/ESITEST0/A8/C8
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1.3/TA1.2/ESITEST4/A3/C3
DVCC2
DVSS2
P7.3/TA0.2/S10
P7.2/TA0.1/S11
P7.1/TA0.0/S12
P7.0/TA0CLK/S13
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S14
On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
On devices with I²C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-2. 80-Pin PN Package (Top View)
Copyright © 2014–2015, Texas Instruments Incorporated
Terminal Configuration and Functions
9
Submit Documentation Feedback
Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887