TMDS171 Datasheet, PDF (9/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

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TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
6.6 Switching Characteristics
The Maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C temperature. The Typical rating is simulated at
3.3 V V_CC and 1.2 V V_DD and at 27°C temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TMDS Redriver Mode
D_R
Data rate (Redriver mode)
250
t_PLH
Propagation delay time (low to high)
250
t_PHL
Propagation delay time (high to low)
250
t_T1
Transition time (rise and fall time);
measured at 20% and 80% levels
for Data Lanes.
TX_TERM_CTL=L; PRE_SEL=NC;
Data Rate 3.4 Gbps; Clock 340 MHz
75
3400
600
800
Mbps
ps
t_SK1(T)
Intra-pair output skew
TX_TERM_CTL=NC;
PRE_SEL=NC;
40
t_SK2(T)
Inter-pair output skew
TX_TERM_CTL=NC;
PRE_SEL=NC;
100
t_JITD1
t_JITC1
Total output data jitter
Total output clock jitter
DR = 750 Mbps, PRE_SEL = NC,
EQ_SEL/A0 = NC. See Figure 5 at
TTP3
0.2
Tbit
0.25
TMDS Retimer Mode
D_R
d_(XVR)
f_(CROSSOVE
R)
PLL_(BW)
t_ACQ
Data rate (retimer mod )
Automatic redriver to Retimer Cross-
Over
Crossover frequency hysteresis
Data Retimer PLL bandwidth
Input Clock Frequency Detection
and Retimer Acquisition Time
Measured with input signal applied
from 0 to 200 mV_PP
Default loop bandwidth setting
1.2
3.4 Gbps
0.75
1.00
1.25 Gbps
250
MHz
0.4
1 MHz
180
µs
I_JT1
Input Clock Jitter Tolerance
Tested when data rate > 1.0 Gbps
Transition time (rise and fall time);
t_T1
measured at 20% and 80% levels
75
for Data Lanes. TMDS
0.3 Tbit
ps
t_DCD
OUT_CLK ± duty cycle
t_{SK_INTER} Inter-pair output skew
Default setting for internal inter-pair
skew adjust, PRE_SEL = NC;
TX_TERM_CTL = NC, DR ≤ 3.4
Gbps; See Figure 6
40%
50%
60%
0.2 Tch
t_{SK_INTRA} Intra-pair output skew
Default setting for internal intra-pair
skew adjust, PRE_SEL = NC;
TX_TERM_CTL = NC, DR ≤ 3.4
Gbps; See Figure 6
0.15 Tbit
t_JITC2
t_JITD2
HPD
Total output clock jitter
Total output data jitter
CLK Rate ≤ 340 MHz
DR ≤ 3.4 Gbps; See Figure 11
0.25 Tbit
0.2 Tbit
t_PD(HPD)
Propagation delay from HPD_SNK
to HPD_SRC; rising edge and falling
edge ⁽¹⁾
see Figure 13; not valid during
switching time
40
120
ns
t_T(HPD)
HPD logical disconnected timeout
DDC and I2C
see Figure 14
2
ms
t_r
Rise time of both SDA and SCL
signals
V_CC = 3.3 V
t_f
Fall time of both SDA and SCL
signals
300
ns
300
t_HIGH
t_LOW
t_SU1
Pulse duration, SCL high
Pulse duration, SCL low
Setup time, SDA to SCL
0.6
µs
1.3
100
ns
(1) The Maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD
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