TMDS171 Datasheet, PDF (20/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
8.2 Functional Block Diagram
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HPD_SRC
VBIAS
50Q
IN_CLKp
IN_CLKn
VBIAS
50Q
EQ
50Q
50Q
IN_D[2:0]p
EQ
IN_D[2:0]n
SIGNAL DETECT
SIG_EN
SIG_DET_OUT
Data Registers
SWAP
PLL
PLL Control
SERDES
190<Q
TMDS
TMDS
HPD_SNK
VSADJ
OUT_CLKp
OUT_CLKn
OUT_D[2:0]p
OUT_D[2:0]n
I2C_EN/PIN
EQ_SEL/A0
A1
SDA_CTL
SCL_CTL
EQ_CTL
EQ_SEL
A0
A1
Control Block, I2C Registers
TERM_SEL
PRE_SEL
Enable
SIG_EN
SIG_DET_OUT
Local I2C
Control
SIG_EN
PRE_SEL
OE
TX_TERM_CTL
SWAP/POL
SDA_SRC
SCL_SRC
SPDIF_IN
ARC_OUT
ARC Function
ACTIVE DDC BLOCK
1.2V
VREG ^3.3V
SDA_SNK
SCL_SNK
GND
VDD
VCC
8.3 Feature Description
8.3.1 Reset Implementation
When OE is de-asserted, control signal inputs are ignored; the HDMI inputs and outputs are high impedance. It
is critical to transition the OE from a low level to high after the V_CC supply has reached the minimum
recommended operating voltage. This is achieved by a control signal to the OE input, or by an external capacitor
connected between OE and GND. To insure the TMDS171 is properly reset, the OE pin must be de-asserted for
at least 100 μs before being asserted. When OE is re-asserted the TMDS171 will have to be reprogrammed if it
was programmed by I²C and not pin strapping. When implementing the external capacitor, the size of the
external capacitor depends on the power up ramp of the V_CC supply, where a slower ramp-up results in a larger
value external capacitor. Refer to the latest reference schematic for TMDS171; consider approximately 200 nF
capacitor as a reasonable first estimate for the size of the external capacitor. Both OE implementations are
shown in Figure 21 and Figure 22.
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