TMDS171 Datasheet, PDF (33/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

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TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
8.5.6 CSR BIT Field Definitions – Misc Control (offset: 00001011) (reset: 00h)
Figure 34. CSR Bit Field Definitions – Misc Control (0Bh)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R/W/U
R/W/U
R/W
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 10. CSR Bit Field Definitions – Misc Control (0Bh)
Bit Field
7:5 Reserved
4:3 TX_TERM_CTL
2
DDC_DR_SEL
1:0 Reserved
Type
R
RWU
R/W
R
Reset
2’b000
2’b00
1’b0
2’b00
Description
Reserved
Controls termination for HDMI TX; Writes are ignored when
I2C_EN/PIN = 0
00 – No termination
01 – 150 to 300 Ω
10 – Reserved.
11 – Reserved
Defines the DDC output speed for both DDC bridge and AUX-
DDC Bridge.
0 = 100 kbps (default)
1 = 400 kbps
Reserved
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