TMDS171 Datasheet, PDF (23/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

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TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
SWAP/POL
1
DATA LANE2 ^IN_D2p
2
IN_D2n
3
HPD_SRC
4
DATA LANE1 ^IN_D1p
5
IN_D1n
6
GND
7
IN_D0p
DATA LANE0
8
IN_D0n
9
I2C_EN/PIN
10
CLOCK LANE ^IN_CLKp
11
IN_CLKn
12
36
TERM_CTL
35
OUT_D2p
34
OUT_D2n
33
HPD_SNK
32
OUT_D1p
31
OUT_D1n
30
GND
29
OUT_D0p
28
OUT_D0n
27
A1
26
OUT_CLKp
25
OUT_CLKn
SWAP/POL
1
IN_D2p
2
CLOCK LANE
IN_D2n
3
HPD_SRC
4
DATA LANE0
IN_D1p
5
IN_D1n
6
GND
7
DATA LANE1
IN_D0p
8
IN_D0n
9
I2C_EN/PIN
10
DATA LANE2
IN_CLKp
11
IN_CLKn
12
36
TERM_CTL
35
OUT_D2p
34
OUT_D2n
33
HPD_SNK
32
OUT_D1p
31
OUT_D1n
30
GND
29
OUT_D0p
28
OUT_D0n
27
A1
26
OUT_CLKp
25
OUT_CLKn
SWAP = Z
In Normal Working
SWAP = L
In Swap Working
Figure 25. TMDS171 Swap Function
8.3.4 TMDS Inputs
Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each
input data channel contains an adaptive or fixed equalizer to compensate for Inter-Symbol Interference (ISI) due
to cable, connector, and/or board trace losses. The voltage at the TMDS input pins must be limited under the
absolute maximum ratings. TMDS input pins have incorporated failsafe circuits. An unused input channel can be
externally biased to prevent output oscillation by connecting the N input pin to be grounded through a 1-kΩ
resistor and the other pin left open. The input pins can be polarity changed through local I²C register when in
retimer mode.
8.3.5 TMDS Inputs Debug Tools
There are two methods for debugging a system to make sure the inputs to the TMDS171 are valid. A TMDS
error checker is implemented to provide a rough Bit Error Rate per data lane. This allows the system
implementer to determine how the link between the source and TMDS171 is performing on all three data lanes.
See CSR BIT FIELD DEFINITIONS – RX PATTERN VERIFIER CONTROL/STATUS register.
If a high error count is evident the TMDS171 has a way to view the general receiver eye quality. A tool is
available that uses the I²C link to down load the data that can be plotted for an eye diagram. This is available per
data lane. This tool also provides a method to turn on an internal PRBS generator that will transmit a data signal
on the data pins. A clock at the proper frequency is required on the IN_CLK pins to generated the expected
output data rate.
8.3.6 Receiver Equalizer
The equalizer used to clean up inter-symbol interference (ISI) jitter/loss from the bandwidth-limited board traces
or cables. TMDS171 supports fixed receiver equalizer and adaptive equalizer by setting the EQ_SEL/A0 pin or
through I²C. When EQ_SEL/A0 is high, the EQ gain is fixed to 10 dB and when set low the EQ gain is set to 7.5
dB. TMDS171 operates in adaptive equalizer mode when EQ_SEL/A0 pin is left floating. The EQ gain will be
automatically adjusted based on the data rate to compensate for trace or cable loss. Implementers can enable
the various EQ settings through local I²C control.
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