TMDS171 Datasheet, PDF (19/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

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8 Detailed Description
TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
8.1 Overview
The TMDS171 is a digital video interface (DVI) or high-definition multimedia interface (HDMI) retimer. The
TMDS171 supports four TMDS channels, Audio Return Channel (SPDIF_IN/ARC_OUT), Hot Plug Detect, and a
Digital Display Control (DDC) interfaces. The TMDS171 supports signaling rates up to 3.4 Gbps to allow for the
highest resolutions of 4k2k30p 24 bits per pixel and up to WUXGA 12-bit color depth or 1080p with higher
refresh rates. The TMDS171 can automatically configure itself as a re-driver at low data rate (< 1 Gbps) or as a
re-timer above this data rate. For passing compliance and reducing system level design issues several features
have been included such as TMDS output amplitude adjust using an external resistor on the VSADJ pin and
source termination selection control. Device operation and configuration can be programmed by pin strapping or
I²C. Four TMDS171s can be used on one I²C bus when I2C_EN enable and device address set by A0/A1.
To reduce active power the TMDS171 supports dual power supply rails of 1.2 V on V_DD and 3.3 V on V_CC. The
TMDS171 supports several methods of power management. It can enter power down mode using three
methods; (1) HPD is low; (2) Writing an 1 to register 09h[3]; or (3) de-asserting OE. If using OE, the device must
be reprogrammed via I²C if it was originally programmed this way. The SIG_EN pin enables the signal detect
circuit that provides an automatic power-management feature during normal operation. When no valid signal is
present on the inputs the device enters Stand by mode. By disabling the detect circuit the receiver block is
always on which is needed for certain HDMI CTS test. DDC link supports 100 Kbps data rate default and 400
kbps adjustable by software.
TMDS171 supports both fixed EQ gain control or adaptive equalization to compensate for different lengths of
input cables or board traces. The EQ gain can be software adjusted by I²C control or selection between two fixed
values or adaptive equalization by pin strapping EQ_SEL pin. Implementers can use the TX_TERM_CTL pin to
change the transmitter termination impedance for better output performance when working in HDMI1.4b or leave
it floating. When floating the TMDS171 in conjunction with the rate detect will automatically change its output
termination to be compatible with HDMI1.4b requirements.
The TMDS171 supports single ended mode audio return channel. To assist in ease of implementation the
TMDS171 supports receive lane swapping and receive polarity swap. When swapping the input lanes IN_CLK
and IN_D2 swap and IN_D1 and IN_D0 swap with each other. Swap works in both retimer and redriver mode.
Polarity swap will swap the receive pins n and p channel polarity in each lane and is only available during retimer
mode. Both lane swap and polarity swap can be implemented at the same time in retimer mode using I²C
control.
Two versions of the device are offered to support extended commercial temperature range 0ºC to 85ºC
(TMDS171) or industrial operational temperature range from -40ºC to 85ºC (TMDS171I).
Copyright © 2015, Texas Instruments Incorporated
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