TMDS171 Datasheet, PDF (35/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

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TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
8.5.8 CSR BIT Field Definitions – Equalization Control Register (offset: 00001101) (reset: 01h)
Figure 36. CSR BIT Field Definitions – Equalization Control Register (0Dh)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
R
R
R/W
R/W
R/W
R/W
R/W
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 12. CSR BIT Field Definitions – Equalization Control Register (0Dh)
Bit Field
7:6 Reserved
5:3 Data Lane EQ
2:1 Clock Lane EQ
0
Reserved
Type
R
R/W
R/W
R
Reset
2’b00
1’b000
13’b000
1’b1
Description
Reserved
Sets Fixed EQ Values
000 – 0 dB
001 – 4.5 dB
010 – 6.5 dB
011 – 8.5 dB
100 – 10.5 dB
101 – 12 dB
110 – 14 dB
111 – 16.5 dB
- Sets Fixed EQ Values.
00 – 0 dB
01 – 1.5 dB
10 – 3 dB
011 – RSVD
Reserved
8.5.9 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00001110) (reset: 00h)
Figure 37. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Eh)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 13. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Eh)
Bit Field
7:4 PV_SYNC[3:0]
3:0 PV_LD[3:0]
Type
R/W
R/W
Reset
4’b0000
4’b0000
Description
Pattern timing pulse. This field is updated for 8UI once every
cycle of the PRBS generator. 1 bit per lane.
Load pattern-verifier controls into RX lanes. When asserted high,
the PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values
are enabled into the corresponding RX lane. These values are
then latched and held when PV_LD[n] is subsequently de-
asserted low. 1 bit per lane.
8.5.10 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00001111) (reset: 00h)
Figure 38. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Fh)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/U
R/U
R/U
R/U
R/U
R/U
R/U
R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 14. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Fh)
Bit Field
7:4 PV_SYNC[3:0]
3:0 PV_LD[3:0]
Type
R/U
R/U
Reset
4’b0000
4’b0000
Description
Pattern verification mismatch detected. 1 bit per lane.
Pattern search/training in progress. 1 bit per lane.
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