TMDS171 Datasheet, PDF (39/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

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TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
8.5.20 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011001) (reset: 00h)
Figure 48. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (19h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R/U
R/U
R/U
R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 24. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (19h)
Bit Field
7:4 Reserved
3:0 BERT_CNT[11:8]
Type
R
R/U
Reset
4’b0000
4’b0000
Description
Reserved
BERT error count. Lane 0
8.5.21 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011010) (reset: 00h)
Figure 49. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ah)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/U
R/U
R/U
R/U
R/U
R/U
R/U
R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 25. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ah)
Bit Field
7:0 BERT_CNT[19:12].
Type
R/U
Reset
‘h00
Description
BERT error count. Lane 1
8.5.22 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011011) (reset: 00h)
Figure 50. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Bh)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R/U
R/U
R/U
R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 26. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Bh)
Bit Field
7:4 Reserved
3:0 BERT_CNT[23:20]
Type
R
R/U
Reset
4’b0000
4’b0000
Description
Reserved
BERT error count. Lane 1
8.5.23 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011100) (reset: 00h)
Figure 51. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ch)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/U
R/U
R/U
R/U
R/U
R/U
R/U
R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 27. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ch)
Bit Field
7:0 BERT_CNT[31:24]
Type
R/U
Reset
‘h00
Description
BERT error count. Lane 2
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