TMDS171 Datasheet, PDF (51/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

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HPD_SNK
OE
H
L
L
H
H
H
H
H
H
H
H
H
H
H
INPUTS
SIG_EN
H or L
H or L
H or L
H
H or L
H
H or L
TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
Table 36. Power Up and Operation Timing Requirements
IN_CLK Device Mode HPD_SRC
IN_Dx
SDA/
SCL_CTL
STATUS
OUT_Dx
OUT_CLK
X
X
H
High-Z
Disable
High-Z
X
X
L
High-Z
Active
High-Z
X
X
H
No Valid
TMDS Clock
X
H
No Valid
TMDS Clock
Retimer mode
H
Valid TMDS
Clock
Retimer mode
H
No Valid
TMDS Clock
Redriver
mode
H
High-Z
D0-D2
Disabled
IN_CLK
Active
D0-D2
Disabled
IN_CLK
Active
RX Active
RX Active
Active
Active
Active
Active
Active
High-Z
High-Z
High-Z
TX Active
TX Active
DDC
Disabled
Disabled
Disabled
Active
Active
Active
Active
ARC
Disable
Disable
Disable
Active
Active
Active
Active
Mode
Power Down
Mode
Power Down
Mode
Power Down
Mode by W 1
to 09h[3]
Standby
Mode
(Squelch
waiting)
Standby
Mode
(Squelch
waiting)
Normal
operation
Normal
operation
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