TMDS171 Datasheet, PDF (10/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
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Switching Characteristics (continued)
The Maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C temperature. The Typical rating is simulated at
3.3 V V_CC and 1.2 V V_DD and at 27°C temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
t_ST,STA
t_HD,STA
t_ST,STO
t_(BUF)
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
Bus free time between stop and start
condition
0.6
0.6
0.6
µs
1.3
t_PLH1
t_PHL1
t_PLH2
t_PHL2
Propagation delay time, low-to-high-
level output
Propagation delay time, high-to-low-
level output
Propagation delay time, low-to-high-
level output
Propagation delay time, high-to-low-
level output
Source to Sink:100 kbps pattern;
C_b(Sink) = 400 pF⁽²⁾; see Figure 17
Sink to Source: 100 kbps pattern;
C_b(Source) = 100 pF⁽²⁾; see Figure 18
360
230
ns
250
200
(2) Cb = total capacitance of one bus line in pF
10
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