TMDS171 Datasheet, PDF (7/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

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TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
6.5 Electrical Characteristics
The Maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C temperature. The Typical rating is simulated at
3.3 V_CC and 1.2 V V_DD and at 27°C temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Power Supply
P_(D1) ^{(1) (2)}
P_(D2) ^{(1) (2)}
Device power Dissipation
(Retimer Operation)
Device power Dissipation
(Redriver Operation)
OE = H, V_CC = 3.3 V / 3.465 V, V_DD = 1.2 V / 1.27 V
IN_Dx: VID_PP = 1200 mV, I2C_EN/PIN = L, PRE_SEL=
H, EQ_CTL= H, SDA_CTL/CLK_CTL = 0 V
3.4 Gbps TMDS pattern, V_I = 3.3 V; VSADJ = 7.06 kΩ
675
875 mW
400
600 mW
P_(SD1) ^{(1) (2)}
Device power in Standby
OE = H, V_CC = 3.3 V / 3.465 V
V_DD = 1.2 V / 1.27 V , HPD = H,
No Valid input Signal
50
100 mW
P_(SD2) ^{(1) (2)}
I_CC1 ^{(1) (2)}
I_DD1 ^{(1) (2)}
Device power in PowerDown
V_CC Supply current (TMDS 3.4
Gpbs Retimer Mode)
V_DD Supply current (TMDS 3.4
Gpbs Retimer Mode)
OE = L, V_CC = 3.3 V / 3.465 V
V_DD = 1.2 V / 1.27 V
OE = H, V_CC = 3.3 V / 3.465 V
V_DD = 1.2 V / 1.27 V
IN_Dx: VID_PP = 1200 mV,
3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H,
EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H
10
30 mW
80
140 mA
286
325 mA
I_CC2 ^{(1) (2)}
I_DD2 ^{(1) (2)}
V_CC Supply current (TMDS 3.4
Gpbs Redriver Mode)
V_DD Supply current (TMDS 3.4
Gpbs Redriver Mode)
OE = H, V_CC = 3.3 V / 3.465 V
V_DD = 1.2 V / 1.27 V
IN_Dx: VID_PP = 1200 mV,
3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H,
EQ_CTL = H, SDA_CTL/CLK_CTL = 0V, SLEW_CTL = H
51
mA
188
mA
I_(SD1)
I_(SD2)
Standby current
PowerDown current
OE = H, V_CC = 3.3 V / 3.465 V
V_DD = 1.2 V / 1.27 V
HPD = H: No valid signal on
IN_CLK
OE = L, V_CC = 3.3 V / 3.465 V
V_DD = 1.2 V / 1.27 V
3.3V Rail⁽¹⁾
1.2V Rail
3.3V Rail⁽¹⁾
1.2V Rail
6
15
mA
40
50
2
5
mA
3.5
15
TMDS Differential Input
D_{(R_RX_DATA)}
D_{(R_RX_CLK)}
t_{RX_DUTY}
t_{CLK_JIT}
t_{DATA_JIT}
t_{RX_INTRA}
t_{RX_INTER}
E_QH(D)
TMDS data lanes data rate
TMDS clock lanes clock rate
Input clock duty circle
Input clock jitter tolerance
Input data jitter tolerance
Input intra-pair skew tolerance
Input inter-pair skew tolerance
Fixed EQ gain for data lane
IN_D(0,1,2)n/p
Test the TTP2 See Figure 11
Test at TTP2 when DR =1.6 Gbps See Figure 11
EQ_SEL/A0=H; Fixed EQ gain, test at 3.4 Gbps
0.25
25
40%
112
50%
14
3.4
340
60%
0.3
150
1.8
Gbps
MHz
Tbit
ps
ps
ns
E_QL(D)
E_QZ(D)
Fixed EQ gain for data lane
IN_D(0,1,2)n/p
Adaptive EQ gain for data lane
IN_D(0,1,2)n/p
EQ_SEL/A0=L; Fixed EQ gain, test at 3.4 Gbps
EQ_SEL/A0=NC; adaptive EQ
7.5
2
dB
14
E_Q(C)
R_(INT)
EQ gain for clock lane IN_CLKn/p EQ_SEL/A0=H,LNC
Input differential termination
impedance
0
90
100
115
Ω
TMDS Differential Output
PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750
V_CC -
V_OH
Single-ended high level output
voltage
Mbps; VSadj = 7.06 kΩ
PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97
10mV
V_CC -
Gbps; VSadj = 7.06 kΩ
200mV
Single-ended low level output
PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750
V_CC -
V_OL
voltage No Pre-emphasis, Load is ^{Mbps; VSadj = 7.06 kΩ}
50 Ω pull ups to 3.135 V and
3.465 V
PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97
Gbps; VSadj = 7.06 kΩ
600mV
V_CC -
700mV
V_CC +
10mV
V_CC +
10mV
V
V_CC -
400mV
V_CC -
400mV
(1) I_CC is a direct result of the source design as the TMDS171 integrated receive termination resistor accounts for 85 mA to 100 mA.
(2) 4. I_DD is impacted by ARC usage. Connecting a 500 KΩ resistor to GND at SPDIF reduces the value by more than 20 mA
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