TMDS171 Datasheet, PDF (45/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

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TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
Source Side Application (continued)
9.2.1 Design Requirements
The TMDS171 can be designed into many different applications. In all the applications there are certain
requirements for the system to work properly. Two voltage rails are required in order to support lowest power
consumption possible. OE pin must have a 200 nF capacitor to ground. This pin can be driven by a processor
but the pin needs to change states after voltage rails have stabilized. The best way to configure the device is by
using I²C but pin strapping is also provided as I²C is not available in all cases. As sources may have many
different naming conventions it is necessary to confirm that the link between the source and the TMDS171 are
correctly mapped. A Swap function is provide for the input pins incase signaling if reversed between source and
device. Table 34 provides information on expected values in order to perform properly.
Table 34. Design Parameters
PARAMETER
V_CC
V_DD
Main Link Input Voltage
Control Pin Max Voltage for Low
Control Pin Voltage Range Mid
Control Pin Min Voltage for High
R_(VSADJ) Resistor
VALUE
3.3 V
1.2 V
V_ID = 75 mV_PP to 1.4 V_PP
65 kΩ pulldown
Left Not Connected/Floating
65 kΩ pullup
7.06 kΩ 1%
9.2.2 Detailed Design Procedure
The TMDS171 is a signal conditioning device that provides several forms of signal conditioning in order to
support compliance for HDMI or DVI at a source connector. These forms of signal conditioning are accomplished
using receive equalization, retiming, and output driver configurability. The transmitter will drive 2-3” of board trace
and connector when compliance is required at the connector.
To design in the TMDS171 the following need to be understood for a source side application:
• Determine the loss profile between the GPU/chipset and the HDMI/DVI connector.
• Based upon this loss profile and signal swing determine optimal location for the TMDS171, in order to pass
source electrical compliance. Usually within 2”-3” of the connector
• Use the typical application Figure 57 for information on control pin resistors.
• The TMDS171 has a receiver adaptive equalizer but can also be configured using EQ_SEL control pin.
• Set the VOD, Pre-emphasis, termination, and edge rate levels appropriately to support compliance by using
the appropriate VSADJ resistor value and setting PRE_SEL, and TX_TERM_CTL control pins.
• The thermal pad must be connected to ground.
• See Figure 57 for recommended decouple capacitors from V_CC and V_DD pins to Ground
9.2.3 Application Curves
Figure 58. 1080p Compliance Eye
Figure 59. 4k2k30 Compliance Eye
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