TMDS171 Datasheet, PDF (28/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
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Device Functional Modes (continued)
8.4.3 DDC Functional Description
The TMDS171 solves sink/source level issues by implementing a master/salve control mode for the DDC bus.
When the TMDS171 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it transfers the
data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the
feedback from the downstream device, the TMDS171 pulls up or pulls down the SDA_SRC bus and delivers the
signal to the source.
The DDC link defaults to 100 kbps but can be set to various values including 400 kbps by setting the correct
value to address 22h through the I²C interface. The DDC lines are 5 V tolerant when the device is powered off.
The HPD goes to high impedance when VCC is under low power conditions < 1.5 V.
NOTE
The TMDS171 utilizes clock stretching for DDC transactions. As there are sources and
sinks that do not perform this function correctly as system may not work correctly as DDC
transactions are incorrectly transmitted/recieved. To overcome this a snoop configuration
can be implemented where the SDA/SCL from the source is connected directly to the
SDA/SCL sink. The TMDS171 will need its SDA_SNK and SCL_SNK pins connected to
this link.
8.4.4 Mode Selection Functional Description
Mode Selection Definition: reg0Ah[7] is the mode select register, see Table 9. This bit lets the receiver know
where the device is located in a system for the purpose of centering the AEQ point. The TMDS171 is targeting
sink or dock applications so the default value is 1 which centers the EQ at 12 dB to 13 dB, see Table 12. If the
TMDS171 is in a source application the value should be changed to a 0 which centers the EQ at 6.5 dB to 7.5
dB.
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