 English |
|
|
|
|
|
|
|
| TMDS171 Datasheet, PDF (8/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER | |||
| |||
| ◁ |
TMDS171, TMDS171I
SLLSEN7A â OCTOBER 2015 â REVISED DECEMBER 2015
www.ti.com
Electrical Characteristics (continued)
The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at
3.3 VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V(SWING_DA)
Single-ended output voltage
swing on data lane
PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC;
DR = ⤠3.4 Gbps; VSadj = 7.06 kΩ
400
500
600
V(SWING_CLK)
Single-ended output voltage
swing on clock lane
PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC;
DR = ⤠3.4 Gbps; VSadj = 7.06 kΩ
400
500
600
ÎV(SWING)
Change in single-end output
voltage swing per 100Ω ÎVSadj
20
ÎVOCM(SS)
Change in steady state output
common mode voltage between
logic levels
â5
5 mV
VOD(PP)
Initial output differential voltage
before steady state when pre-
emphasis or de-emphasis is
implemented
VSadj = 7.06 kΩ; PRE_SEL = NC, See Figure 8
800
1200
VOD(SS)
Steady state output differential
voltage
VSadj = 7.06 kΩ; PRE_SEL = L, See Figure 9
600
1075
IOS
ILEAK
Short circuit current limit
Main link output shorted to GND
Failsafe condition leakage current
VCC = 0 V; VDD = 0 V; TMDS Outputs pulled to 3.3V through
50 Ω resistor
50 mA
45 µA
R(TERM)
DDC and I2C
Source Termination resistance
150
300
Ω
VIL
SCL/SDA_CTL, SCL/SDA_SRC
low level input voltage
0.3xVCC
VIH
SCL/SDA_CTL, SCL/SDA_SRC
high level input voltage
0.7xVCC
VCC +
0.5
V
VOL
HPD
SCL/SDA_CTL, SCL/SDA_SRC
low level output voltage
IO = 3 mA and VCC > 2 V
IO = 3 mA and VCC < 2 V
0.4
0.2xVCC
VIH
VIL
VOH
VOL
ILEAK
IH(HPD)
High-level input voltage
HPD_SNK
2.1
Low-level input voltage
HPD_SNK
High-level output voltage
IOH = -500 µA; HPD_SRC
2.4
Low-level output voltage
IOL = -500 µA; HPD_SRC
0
Failsafe condition leakage current VCC = 0 V; VDD = 0 V; HPD_SNK = 5 V
High level input current
Device powered; VIH = 5 V; IH(HPD) includes Rpd(HPD) resistor
current
Device powered; VIL = 0.8 V; IH(HPD) includes Rpd(HPD)
resistor current
0.8
3.6
V
0.1
40
40
µA
30
Rpd(HPD)
HPD input termination to GND;
SPDIF and ARC
VCC < 0 V
150
190
220 kΩ
V(EL)
Operating DC voltage for single
mode ARC output
Test at ARC_OUT, see Figure 19
0
5
V
VIN(DC)
Operating DC voltage for SPDIF
input
0.05
V
V(SP_SW)
V(ElSWING)
Signal amplitude of SPDIF input
Signal amplitude on the ARC
output
Test at ARC_OUT, 75 Ω external termination resistor, see
Figure 19
0.2
0.5
0.6
V
0.4
0.5
0.6
V
CLK(ARC)
Signal frequency on ARC
Test at ARC_OUT, see Figure 19
3.687
5.645±0.
1%
13.517
MHz
Duty Cycle
Output Clock Duty cycle
45%
50%
55%
Data Rate
SPDIF Input DR
7.373 11.29 27.034 Mbps
tEDGE
R(IN_SPDIF)
The rise/fall time for ARC output
The Input Termination resistance
for SPDIF
From 10% to 90% voltage level, see Figure 19
0.4 UI
75
Ω
R(EST)
Single mode Output Termination
resistance
0.1 MHz to 128 times the maximum frame rate
36
55
75
Ω
8
Submit Documentation Feedback
Product Folder Links: TMDS171
Copyright © 2015, Texas Instruments Incorporated
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese