TMDS171 Datasheet, PDF (38/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
www.ti.com
8.5.17 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010110) (reset: 00h)
Figure 45. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (16h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 21. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (16h)
Bit Field
7:4 PV_DP_EN[3:0]
3
Reserved
2:0 DP_TST_SEL[2:0]
Type
R/W
R
R/W
Reset
4’b0000
1’b0
3’b000
Description
Enable datapath verified based on DP_TST_SEL, 1 bit per lane
Reserved
Selects pattern reported by BERT_CNT[11:0],
TST_INT[0] and TST_INTQ[0] and PV_DP_EN is non-zero.
000 – TMDS disparity or data errors
001 – FIFO errors
010 – FIFO overflow errors
011 – FIFO underflow errors
100 – TMDS deskew status
101,110,111 – Reserved.
8.5.18 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010111) (reset: 00h)
Figure 46. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (17h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/U
R/U
R/U
R/U
R/U
R/U
R/U
R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 22. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (17h)
Bit Field
7:4 TST_INTQ[3:0]
3:0 RTST_INT[3:0]
Type
R/U
R/U
Reset
4’b0000
4’b0000
Description
Latched interrupt flag. 1 bit per lane
Test interrupt flag. 1 bit per lane.
8.5.19 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011000) (reset: 00h)
Figure 47. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (18h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/U
R/U
R/U
R/U
R/U
R/U
R/U
R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 23. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (18h)
Bit Field
7:0 BERT_CNT[7:0]
Type
R/U
Reset
‘h00
Description
BERT error count. Lane 0
38
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