TMDS171 Datasheet, PDF (29/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

www.ti.com
TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
8.5 Register Maps
8.5.1 Local I²C Overview
The TMDS171 local I²C interface is enabled when I2C_EN/PIN is high. The SCL_CTL and SDA_CTL terminals
are used for I²C clock and I²C data respectively. The TMDS171 I²C interface conforms to the two-wire serial
interface defined by the I²C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer
up to 400 kbps.
The device address byte is the first byte received following the START condition from the master device. The 7
bit device address for TMDS171 decides by the combination of EQ_SEL/A0 and A1. Table 4 clarifies the
TMDS171 target address.
A1/A0
00
01
10
11
Bit 7 (MSB)
1
1
1
1
Table 4. TMDS171 I2C Device Address Description
Bit 6
0
0
0
0
Bit 5
1
1
1
1
TMDS171 I2C Device Address
Bit 4
Bit 3
1
1
1
1
1
1
1
0
Bit 2
1
0
0
1
Bit 1
0
1
0
1
Bit 0 (W/R)
0/1
0/1
0/1
0/1
HEX
BC/BD
BA/BB
B8/B9
B6/B7
The typical source application of the TMDS171 is as a retimer in a TV connecting the HDMI input connector and
an internal HDMI receiver through flat cables. The register setup can adjust by source side. When TMDS171
used in sink side application, it received data from input connector and transmit to receiver. The local I²C is not 5
V tolerant and only support 3.3 V. Local I2C buses run at 400 kHz supporting fast-mode I²C operation.
The following procedure is followed to write to the TMDS171 I²C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the TMDS171 7-bit
address and a zero-value “W/R” bit to indicate a write cycle
2. The TMDS171 acknowledges the address cycle
3. The master presents the sub-address (I²C register within TMDS171) to be written, consisting of one byte of
data, MSB-first
4. The TMDS171 acknowledges the sub-address cycle
5. The master presents the first byte of data to be written to the I²C register
6. The TMDS171 acknowledges the sub-address cycle
7. TMDS171 acknowledges the byte transfer
8. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TMDS171
9. The master terminates the write operation by generating a stop condition (P)
The following procedure is followed to read the TMDS171 I²C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the TMDS171 7-bit
address and a one-value “W/R” bit to indicate a read cycle
2. The TMDS171 acknowledges the address cycle
3. The TMDS171 transmit the contents of the memory registers MSB-first starting at register 00h.
4. The TMDS171 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after
each byte transfer; the I²C master acknowledges reception of each data byte transfer
5. If an ACK is received, the TMDS171 transmits the next byte of data
6. The master terminates the read operation by generating a stop condition (P)
NOTE
Nno sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I²C master terminates the
read operation.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TMDS171
Submit Documentation Feedback
29