TMDS171 Datasheet, PDF (31/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

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TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
8.5.4 CSR BIT Field Definitions – Misc Control (offset: 00001001) (reset: 02h)
Figure 32. CSR Bit Field Definitions – Misc Control (09h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
R/W/U
R/W/U
R
R/W/U
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 8. CSR Bit Field Definitions – Misc Control (09h)
Bit Field
7
Lane_SWAP
6
LANE_POLARITY
5
Reserved
4
SIG_EN
Type
R/W/U
Reset
1’b0
R/W/U 1’b0
R
1’b0
R/W/U 1’b0
3
PD_EN
R/W
1’b0
2
HPD_AUTO_PWRDWN_DISABLE R/W
1’b0
1:0 I2C_DR_CTL
R/W
2’b10
Description
This field Swaps the input lanes as per Figure 25.
0 --- Disable (default) No Lane Swap
1 --- enable: Swaps input lanes (Redriver and Retimer Mode)
Note: field is loaded from SWAP/POL pin; Writes are ignored
when I2C_EN/PIN = 0
Swaps the input Data and Clock lanes polarity.
0 – Disabled: No polarity swap
1 – Swaps the input Data and Clock lane polarity (Retimer Mode
Only)
Note: field is loaded from SWAP/POL pin; Writes are ignored
when I2C_EN/PIN = 0
Reserved
This field enable the clock lane activity detect circuitry.
0 – Disable(Default) Clock detector circuit closed and receiver
always works in normal operation.
1 – Enable , Clock detector circuit will make receiver automatic
enter the standby state when no valid data detect.
Note: field is loaded from SIG_EN pin; Writes are ignored when
I2C_EN/PIN = 0
0 – Normal working (default)
1 – Forced Power down by I²C, Lowest Power state
0 – Automatically enters power down mode based on HPD_SNK
(default)
1 – Will not automatically enter power down mode
I²C data rate supported for configuring device.
00 – 5 Kbps
01 – 10 Kbps
10 – 100 Kbps(default)
11 – 400 Kbps
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