TMDS171 Datasheet, PDF (34/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
www.ti.com
8.5.7 CSR BIT Field Definitions – Misc Control (offset: 00001100) (reset: 00h)
Figure 35. CSR Bit Field Definitions – Misc Control (0Ch)
7
6
5
4
3
2
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
1
0
R/W/U
0
0
R/W/U
Table 11. CSR Bit Field Definitions – Misc Control (0Ch)
Bit Field
7:5 VSWING_DATA
4:2 VSWING_CLK
1:0 HDMI_TWPST1[1:0]
Type
R/W
R/W
R/W/U
Reset
3’b000
13’b000
2’b00
Description
Data Output Swing Control (Need Design input on what is
available)
000 – Vsadj set (default)
001 – Increase by 7%
010 – Increase by 13%
011 – Increase by 18%
100 – Decrease by 30%
101 – Decrease by 22%
110 – Decrease by 15%
111 – Decrease by 7%
Clock Output Swing Control: Default is set by DR which means
standard based swing values but this allows for the swing to be
overridden by selecting one of the following values.
000 – Set by Data Rate
001 – Increase by 7%
010 – Increase by 13%
011 – Increase by 18%
100 – Decrease by 30%
101 – Decrease by 22%
110 – Decrease by 15%
111 – Decrease by 7%
HDMI pre-emphasis FIR post-cursor-1 signed tap weight.
00 – No pre-emphasis
01 – 2 dB pre-emphasis.
10 – Reserved
11 – Reserved
Note: Reflects value of PRE_SEL pin; Writes are ignored when
I2C_EN/PIN = 0
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