TMDS171 Datasheet, PDF (48/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
9.2.4.1 Design Requirements
See Table 35 for the Sink Side design example parameters.
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Table 35. Design Parameters
PARAMETER
V_CC
V_DD
Main Link Input Voltage
Control Pin Max Voltage for Low
Control Pin Voltage Range Mid
Control Pin Min Voltage for High
R_(VSADJ) Resistor
VALUE
3.3 V
1.2 V
V_ID = 75 mV_PP to 1.4 V_PP
65 kΩ pulldown
Left Not Connected/Floating
65 kΩ pullup
7.06 kΩ 1%
9.2.4.2 Detailed Design Procedure
To design in the TMDS171 the following need to be understood for a source side application.
• Determine the loss profile between the RX/chipset and the HDMI/DVI connector.
• Based upon this loss profile and signal swing determine optimal location for the TMDS171, in order to pass
sink electrical compliance.
• Use the typical application Figure 56 for information on control pin resistors.
• The TMDS171 has a receiver adaptive equalizer but can also be configured using EQ_SEL control pin.
• Set the VOD, Pre-emphasis, termination, and edge rate levels appropriately to support link between
TMDS171 and HDMI RX/Chipset by using the appropriate VSADJ resistor value and setting PRE_SEL and
TX_TERM_CTL control pins.
• The thermal pad must be connected to ground.
• See Figure 60 for recommended decouple caps from V_CC and V_DD pins to Ground.
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