TMDS171 Datasheet, PDF (36/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
www.ti.com
8.5.11 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010000) (reset: 00h)
Figure 39. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (10h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 15. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (10h)
Bit Field
7
PV_CP20
6
Reserved
5:3 PV_LEN[2:0]
2:0 PV_SEL[24:0]
Type
R/W
R
R,W
R/W
Reset
1’b0
1’b0
3’b000
3’b000
Description
Customer pattern length 20/16 bits.
0 – 16 bits
1 – 20 bits
Reserved
]PRBS pattern length
000 – PRBS7
001 – PRBS11
010 – PRBS23
011 – PRBS31
100 – PRBS15
101 – PRBS15
110 – PRBS20
111 – PRBS20
Pattern select control
000 – Disabled
001 – PRBS
010 - Clock
011 - Custom
1xx – Timing only mode with sync pulse spacing defined by
PV_LEN
8.5.12 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010001) (reset: 00h)
Figure 40. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (11h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 16. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (11h)
Bit Field
7
PV_CP[7:0]
Type
R/W
Reset
‘h00
Description
Custom pattern data.
8.5.13 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010010) (reset: 00h)
Figure 41. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (12h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 17. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (12h)
Bit Field
7
PV_CP[15:8]
Type
R/W
Reset
‘h00
Description
Custom pattern data.
36
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