TMDS171 Datasheet, PDF (4/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
PIN
NAME
NO.
VCC
13, 43
VDD
14, 23, 24, 37, 48
GND
7, 19, 27, 41, 30
Thermal Pad
MAIN LINK INPUT PINS (FAILAFE)
IN_D2p/n
2, 3
IN_D1p/n
5, 6
IN_D0p/n
8, 9
IN_CLKp/n
11, 12
MAIN LINK OUTPUT PINS (FAILAFE)
OUT_D2n/p
34, 35
OUT_D1n/p
31, 32
OUT_D0n/p
28, 29
OUT_CLKn/p
25, 26
HOT PLUG DETECT PINS
HPD_SRC
4
HPD_SNK
33
AUDIO RETURN CHANNEL and DDC PINS
SPDIF_IN
45
ARC_OUT
44
SDA_SRC
47
SCL_SRC
46
SDA_SNK,
39
SCL_SNK
38
CONTROL PINS⁽²⁾
OE
42
I/O ⁽¹⁾
P
P
G
G
I
I
I
I
O
O
O
O
O
I
I
O
I/O
I/O
I/O
I/O
I
SIG_EN
17
I
PRE_SEL
20
I
3-Level
EQ_SEL/A0
I2C_EN/PIN
SCL_CTL
SDA_CTL
VSadj
21
I
10
I
15
I/O
16
I/O
22
I
Pin Functions
3.3 V Power Supply
1.2 V Power Supply
Ground
Ground
DESCRIPTION
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Channel 2 Differential Input
Channel 1 Differential Input
Channel 0 Differential Input
Clock Differential Input
TMDS Data 2 Differential Output
TMDS Data 1 Differential Output
TMDS Data 0 Differential Output
TMDS Clock Differential Output
Hot Plug Detect Output to source side
Hot Plug Detect Input from sink side
SPDIF signal input
Audio return channel output
Source Side TMDS Port Bidirectional DDC Data line
Source Side TMDS Port Bidirectional DDC Clock line
Sink Side TMDS Port Bidirectional DDC Data Line
Sink Side TMDS Port Bidirectional DDC Clock Line
Operation Enable/Reset Pin
OE = L: Power Down Mode
OE = H: Normal Operation
Internal weak pull up: Resets device when transitions from H to L
Signal detector circuit enable
SIG_EN = L: Signal Detect Circuit Disabled: Term resistors always connected (Default)
SIG_EN = H: Signal Detect Circuit Enabled: When no valid clock device enters Standby
Mode.
Internal weak pull down
De-emphasis Control when I2C_EN/PIN = Low.
PRE_SEL = L: -2 dB
PRE_SEL = No Connect: 0 dB
PRE_SEL = H: Reserved
When I2C_EN/PIN = High; De-emphasis is controlled through I²C
Input Receive Equalization pin strap when I2C_EN/PIN = Low
EQ_SEL = L: Fixed EQ at 7.5 dB
EQ_SEL = No Connect: Adaptive EQ
EQ_SEL = H: Fixed at 14 dB
When I2C_EN/PIN = High Address Bit 1
Note: 3 level for pin strap programming but 2 level when I²C address
I2C_EN/PIN = High; Puts Device into I2C Control Mode
I2C_EN/PIN = Low; Puts Device into Pin Strap Mode
I²C Clock Signal when I²C_EN/PIN = High.
Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be
changed by I²C
I²C Data Signal when I²C_EN/PIN = High
Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be
changed by I²C
TMDS Output Voltage Swing Control; Nominal 7.06 kΩ Resistor to GND
(1) (1) G = Ground, I = Input, O = Output, P = Power
(2) (H) Logic High (Pin strapped to VCC through 65 kΩ resistor); (L) Logic Low (Pin strapped to GND through 65 kΩ resistor); (Mid-Level =
No connect)
4
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