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TMDS171 Datasheet, PDF (32/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER
TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
www.ti.com
8.5.5 CSR BIT Field Definitions – Misc Control (offset: 00001010) (reset: B1h)
Figure 33. CSR Bit Field Definitions – Misc Control (0Ah)
7
6
5
4
3
2
1
0
1
0
1
1
0
0
0
1
R/W
R/W
R/W
R/W
R
W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 9. CSR Bit Field Definitions – Misc Control (0Ah)
Bit Field
7
Application Mode Selection
6
HPDSNK_GATE_EN
5
EQ_ADA_EN
4
EQ_EN
3
Reserved
2
APPLY_RXTX_CHANGES
1:0 DEV_FUNC_MODE.
Type
R/W
Reset
1’b1
R/W
1’b0
R/W
1’b1
R/W
1’b1
R
1’b0
W
1’b0
R/W
2’b01
Description
See Mode Selection
TMDS171
0 – Source
1 – Sink (Default)
Swaps the input Data and Clock lanes polarity. The field set the
HPD_SNK signal pass through to HPD_SRC or not and
HPD_SRC whether held in the de-asserted state.
0 – HPD_SNK passed through to the HPD_SRC ( default )
1 – HPD_SNK will not pass through to the HPD_SRC.
This field enable the equalizer functioning state; Writes are
ignored when I2C_EN/PIN = 0
0 – Fixed EQ
1 – Adaptive EQ (default)
This field enable the Equalizer; Writes are ignored when
I2C_EN/PIN = 0
0 -- EQ disable
1 – EQ enable (default)
Reserved
Self-clearing write-only bit.
Writing a 1 to this bit will apply new TX_TERM, HDMI_TWPST1,
EQ_EN, EQ_ADA_EN, VSWING, Fixed EQ value settings to the
clock and data lanes. Writes to the respective registers do not
take immediate effect.
This bit does not need to be written if I2C configuration occurs
while OE or HPD_SNK are low, I2C PD_EN=1 or there is no
HDMI clock applied and SIG_EN is high.
This field selects the Device Working Function Mode.
00 – Redriver Mode across full range 250 Mbps – 3.4 Gbps
01 - Automatic Redriver to Retimer Cross Over at 1.0 Gbps
(default)
10 - Reserved
11 - Retimer Mode across full range 250 Mbps – 3.4 Gbps
When changing crossover point, need to toggle PD_EN or
toggle external HPD_SNK.
32
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