TMDS171 Datasheet, PDF (22/62 Pages) Texas Instruments – 3.4 Gbps TMDS RETIMER

TMDS171, TMDS171I
SLLSEN7A – OCTOBER 2015 – REVISED DECEMBER 2015
Feature Description (continued)
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CDR Active
Retimer mode
Td3
Td4
Figure 24. CDR Timing for TMDS171
OE De-assert or
HPD_SNK De-assert or
Redriver mode
t_d1
t_d2
t_d3
td4
V_DD(ramp)
V_CC(ramp)
Table 1. Power Up and Operation Timing Requirements
DESCRIPTION
V_DD Stable before V_CC
V_DD and V_CC stable before OE de-assertion
CDR active operation after retimer mode initiated
CDR turn off time after retimer mode de-assert
V_DD supply ramp up requirements
V_CC supply ramp up requirements
MIN
TYP
0
100
0.2
0.2
MAX
200
15
120
100
100
UNIT
µs
ms
ns
ms
ms
8.3.3 Swap and Polarity Working (Retimer Mode Only)
TMDS171 incorporates swap function which can set the input lanes in swap mode. The IN_D2 will route to the
OUT_CLK position by swapping with IN_CLK. The IN_D1 swaps with IN_D0. The Swap function only changes
the input pins. The EQ setup follows the new mapping, see Figure 25. This function can be used with the
SWAP/POL pin 1 and control the register 0x09h bit 7 for SWAP enable. The Swap function works in both redriver
and retimer mode. The TMDS171 can also swap the input polarity signals. When SWAP/POL is high the n and p
pins on each lane will swap. Polarity swap only works when in retimer mode. When this function is enabled and
the device is in automatic cross over mode between redriver and retimer modes, care must be taken to avoid
losing polarity swap. When the data rate drops to the redriver level, the polarity swap is lost.
Normal Op
IN_D2 → OUT_D2
IN_D1 → OUT_D1
IN_D0 → OUT_D0
IN_CLK → OUT_CLK
Table 2. SWAP Pin Mapping
SWAP = L or CSR 0x09h bit 7 is 1'b1
IN_D2 → OUT_CLK
IN_D1 → OUT_D0
IN_D0 → OUT_D1
IN_CLK → OUT_D2
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