SM320C6727B-EP Datasheet, PDF (9/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
www.ti.com
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
Table 2-2. New Floating-Point Instructions for C67x+ CPU
INSTRUCTION
FLOATING-POINT
OPERATION ⁽¹⁾
IMPROVES
MPYSPDP
SP x DP → DP
Faster than MPYDP.
Improves high Q biquads (bass management) and FFT.
MPYSP2DP
SP x SP → DP
Faster than MPYDP.
Improves Long FIRs (EQ).
ADDSP (new to CPU “S” Unit)
SP + SP → SP
ADDDP (new to CPU “S” Unit)
SUBSP (new to CPU “S” Unit)
DP + DP → DP
SP – SP → SP
Now up to four floating-point add and subtract operations in parallel.
Improves FFT performance and symmetric FIR.
SUBDP (new to CPU “S” Unit)
DP – DP → DP
(1) SP means IEEE Single-Precision (32-bit) operations and DP means IEEE Double-Precision (64-bit) operations.
Finally, two new registers, which are dedicated to communication with the dMAX unit, have been added to
the C67x+ CPU. These registers are the dMAX Event Trigger Register (DETR) and the dMAX Event
Status Register (DESR). They allow the CPU and dMAX to communicate without requiring any accesses
to the memory system.
2.3 CPU Interrupt Assignments
Table 2-3 lists the interrupt channel assignments on the C672x device. If more than one source is listed,
the interrupt channel is shared and an interrupt on this channel could have come from any of the enabled
peripherals on that channel.
The dMAX peripheral has two CPU interrupts dedicated to reporting FIFO status (INT7) and transfer
completion (INT8). In addition, the dMAX can generate interrupts to the CPU on lines INT9–13 and INT15
in response to peripheral events. To enable this functionality, the associated Event Entry within the dMAX
can be programmed so that a CPU interrupt is generated when the peripheral event is received.
CPU INTERRUPT
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
INT13
INT14
INT15
Table 2-3. CPU Interrupt Assignments
INTERRUPT SOURCE
RESET
NMI (From dMAX or EMIF Interrupt)
Reserved
Reserved
RTI Interrupt 0
RTI Interrupts 1, 2, 3, and RTI Overflow Interrupts 0 and 1.
UHPI CPU Interrupt (from External Host MCU)
FIFO status notification from dMAX
Transfer completion notification from dMAX
dMAX event (0x2 specified in the dMAX interrupt event entry)
dMAX event (0x3 specified in the dMAX interrupt event entry)
dMAX event (0x4 specified in the dMAX interrupt event entry)
dMAX event (0x5 specified in the dMAX interrupt event entry)
dMAX event (0x6 specified in the dMAX interrupt event entry)
I2C0, I2C1, SPI0, SPI1 Interrupts
dMAX event (0x7 specified in the dMAX interrupt event entry)
Copyright © 2011, Texas Instruments Incorporated
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