SM320C6727B-EP Datasheet, PDF (72/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
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Figure 4-28 shows the bit layout of the CFGMCASP0 register and Table 4-19 contains a description of the
bits.
31
8
Reserved
7
3
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
0
AMUTEIN0
R/W, 0
Figure 4-28. CFGMCASP0 Register Bit Layout (0x4000 0018)
Table 4-19. CFGMCASP0 Register Bit Field Description (0x4000 0018)
BIT NO.
NAME
31:3 Reserved
2:0 AMUTEIN0
RESET
VALUE
N/A
0
READ
WRITE
N/A
R/W
DESCRIPTION
Reads are indeterminate. Only 0s should be written to these bits.
AMUTEIN0 Selects the source of the input to the McASP0 mute input.
000 = Select the input to be a constant '0'
001 = Select the input from AXR0[7]/SPI1_CLK
010 = Select the input from AXR0[8]/AXR1[5]/SPI1_SOMI
011 = Select the input from AXR0[9]/AXR1[4]/SPI1_SIMO
100 = Select the input from AHCLKR2
101 = Select the input from SPI0_SIMO
110 = Select the input from SPI0_SCS/I2C1_SCL
111 = Select the input from SPI0_ENA/I2C1_SDA
72
Peripheral and Electrical Specifications
Copyright © 2011, Texas Instruments Incorporated
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