SM320C6727B-EP Datasheet, PDF (58/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
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Figure 4-19 illustrates the Non-Multiplexed Host Address/Data Fullword mode of the UHPI. In this mode,
the UHPI behaves almost like an asynchronous SRAM except it asserts the UHPI_HRDY signal. This
mode allows the host to randomly access a 64K-byte page in the C672x address space. The upper 32 bits
of the C672x address are set by the DSP (only) through the CFGHPIAMSB and CFGHPIAUMB registers
(see Table 4-13 and Table 4-14).
DSP
External Host MCU
EM_D[31:16]/UHPI_HA[15:0]
UHPI_HCNTL[1:0]
UHPI_HD[15:0]
UHPI_HD[16]/HHWIL
UHPI_HD[31:17]
UHPI_HAS^(B)
UHPI_HBE[3:0]
UHPI_HRW
UHPI_HDS[2]
UHPI_HDS[1]
UHPI_HCS
UHPI_HRDY
AMUTE2/HINT
A[17:2]
A[x:y]^(A)
D[15:0]
D[16]
D[31:17]
BE[3:0]^(C)
R/W
WE^(D)
RD^(D)
CS
RDY
INTERRUPT
A. Two host address lines or host GPIO if address lines are not available.
B. Not used in this mode.
C. Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write enable
pins.
D. Only required if needed for strobe timing. Not required if CS meets strobe timing requirements.
Figure 4-19. UHPI Non-Multiplexed Host Address/Data Fullword Mode
CAUTION
The EMIF data bus and UHPI HA inputs share the EM_D[31:16]/UHPI_HA[15:0] pins.
When using Non-Multiplexed mode, make sure the EMIF does not drive EM_D[31:16];
otherwise, a drive conflict with the external host MCU may result. Normally, the EMIF
will begin to drive the EM_D[31:16] lines immediately after it completes the SDRAM
initialization sequence, which occurs automatically after RESET is released. To avoid a
drive conflict then, the boot software must set CFGHPI.NMUX to '1' before the EMIF
drives EM_D[31:16]. Setting CFGHPI.NMUX to '1' forces these pins to be input pins.
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Peripheral and Electrical Specifications
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