SM320C6727B-EP Datasheet, PDF (4/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
• Two 32-bit counter/prescaler pairs
• Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement)
• Four compares with automatic update capability
• Digital Watchdog (optional) for enhanced system robustness
Clock Generation (PLL and OSC). The C672x DSP includes an on-chip oscillator that supports crystals
in the range of 12 MHz to 25 MHz. Alternatively, the clock can be provided externally through the CLKIN
pin.
The DSP includes a flexible, software-programmable phase-locked loop (PLL) clock generator. Three
different clock domains (SYSCLK1, SYSCLK2, and SYSCLK3) are generated by dividing down the PLL
output. SYSCLK1 is the clock used by the CPU, memory controller, and memories. SYSCLK2 is used by
the peripheral subsystem and dMAX. SYSCLK3 is used exclusively for the EMIF.
1.2.1 Device Compatibility
The SM320C6727B floating-point digital signal processor is based on the new C67x+ CPU. This core is
code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant
enhancements including additional floating-point instructions. See Section 2.2
4
SM320C6727B DSP
Submit Documentation Feedback
Product Folder Link(s): SM320C6727B-EP
Copyright © 2011, Texas Instruments Incorporated