SM320C6727B-EP Datasheet, PDF (3/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
www.ti.com
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash device
that can be 8, 16, or 32 bits wide. Booting from larger flash devices than are natively supported by the
dedicated EMIF address lines is accomplished by using general-purpose I/O pins for upper address lines.
The asynchronous memory interface can also be configured to support 8- or 16-bit-wide NAND flash. It
includes a hardware ECC calculation (for single-bit errors) that can operate on blocks of data up to
512 bytes.
Universal Host-Port Interface (UHPI) for High-Speed Parallel I/O. The Universal Host-Port Interface
(UHPI) is a parallel interface through which an external host CPU can access memories on the DSP.
Three modes are supported by the C672x UHPI:
• Multiplexed Address/Data - Half-Word (16-bit-wide) Mode (similar to C6713)
• Multiplexed Address/Data - Full Word (32-bit-wide) Mode
• Non-Multiplexed Mode - 16-bit Address and 32-bit Data Bus
The UHPI can also be restricted to accessing a single page (64K bytes) of memory anywhere in the
address space of the C672x; this page can be changed, but only by the C672x CPU. This feature allows
the UHPI to be used for high-speed data transfers even in systems where security is an important
requirement.
The UHPI is only available on the C6727.
Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) - Up to 16 Stereo Channels I2S.
The multichannel audio serial port (McASP) seamlessly interfaces to CODECs, DACs, ADCs, and other
devices. It supports the ubiquitous IIS format as well as many variations of this format, including time
division multiplex (TDM) formats with up to 32 time slots.
Each McASP includes a transmit and receive section which may operate independently or synchronously;
furthermore, each section includes its own flexible clock generator and extensive error-checking logic.
As data passes through the McASP, it can be realigned so that the fixed-point representation used by the
application code can be independent of the representation used by the external devices without requiring
any CPU overhead to make the conversion.
The McASP is a configurable module and supports between 2 and 16 serial data pins. It also has the
option of supporting a Digital Interface Transmitter (DIT) mode with a full 384 bits of channel status and
user data memory.
McASP2 is not available on the C6722.
Inter-Integrated Circuit Serial Ports (I2C0, I2C1). The C672x includes two inter-integrated circuit (I2C)
serial ports. A typical application is to configure one I2C serial port as a slave to an external user-interface
microcontroller. The other I2C serial port may then be used by the C672x DSP to control external
peripheral devices, such as a CODEC or network controller, which are functionally peripherals of the DSP
device.
The two I2C serial ports are pin-multiplexed with the SPI0 serial port.
Serial Peripheral Interface Ports (SPI0, SPI1). As in the case of the I2C serial ports, the C672x DSP
also includes two serial peripheral interface (SPI) serial ports. This allows one SPI port to be configured as
a slave to control the DSP while the other SPI serial port is used by the DSP to control external
peripherals.
The SPI ports support a basic 3-pin mode as well as optional 4- and 5-pin modes. The optional pins
include a slave chip-select pin and an enable pin which implements handshaking automatically in
hardware for maximum SPI throughput.
The SPI0 port is pin-multiplexed with the two I2C serial ports (I2C0 and I2C1). The SPI1 serial port is
pin-multiplexed with five of the serial data pins from McASP0 and McASP1.
Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes:
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