SM320C6727B-EP Datasheet, PDF (102/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
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4.18 Phase-Locked Loop (PLL)
4.18.1 PLL Device-Specific Information
The C672x DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
CLKIN pin. The PLL outputs four clocks that have programmable divider options. Figure 4-45 illustrates
the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in Table 4-40 before enabling the DSP to run from the PLL by setting
PLLEN = 1.
Clock
Input
from
CLKIN or
OSCIN
Divider
D0
(/1 to /32)
PLLREF
PLL
x4 to x25
PLLOUT
1
0
PLLEN
(PLL_CSR[0])
Divider SYSCLK1
D1
CPU and Memory
(/1 to /32)
Divider
D2
(/1 to /32)
SYSCLK2
Peripherals and dMAX
Divider _SYSCLK3
D3
EMIF
(/1 to /32)
Figure 4-45. PLL Topology
AUXCLK
McASP0,1,2
102 Peripheral and Electrical Specifications
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