SM320C6727B-EP Datasheet, PDF (60/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
The UHPI has several device-level configuration registers which affect its behavior. Figure 4-20,
Figure 4-21, and Figure 4-22 show the bit layout of these registers. Table 4-12, Table 4-13, and
Table 4-14 contain a description of the bits in these registers.
31
Reserved
7
5
4
Reserved
BYTEAD
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
FULL
R/W, 0
2
NMUX
R/W, 0
1
PAGEM
R/W, 0
Figure 4-20. CFGHPI Register Bit Layout (0x4000 0008)
8
0
ENA
R/W, 0
Table 4-12. CFGHPI Register Bit Field Description (0x4000 0008)
BIT NO.
NAME
31:5 Reserved
4
BYTEAD
3
FULL
2
NMUX
1
PAGEM
0
ENA
RESET
VALUE
N/A
0
0
0
0
0
READ
WRITE
N/A
R/W
R/W
R/W
R/W
R/W
DESCRIPTION
Reads are indeterminate. Only 0s should be written to these bits.
UHPI Host Address Type
0 = Host Address is a word address
1 = Host Address is a byte address
UHPI Multiplexing Mode (when NMUX = 0)
0 = Half-Word (16-bit data) Multiplexed Address and Data Mode
1 = Fullword (32-bit data) Multiplexed Address and Data Mode
UHPI Non-Multiplexed Mode Enable
0 = Multiplexed Address and Data Mode
1 = Non-Multiplexed Address and Data Mode (utilizes optional UHPI_HA[15:0] pins).
Host data bus is 32 bits in Non-Multiplexed mode. Setting this bit prevents the EMIF
from driving data out or 'parking' the shared EM_D[31:16]/UHPI_HA[15:0] pins.
UHPI Page Mode Enable (Only for Multiplexed Address and Data Mode).
0 = Full 32-bit DSP address specified through host port.
1 = Only lower 16 bits of DSP address are specified through host port. Upper 16 bits
are restricted to the page selected by CFGHPIAMSB and CFGHPIAUMB registers.
UHPI Enable
0 = UHPI is disabled
1 = UHPI is enabled. Set this bit to '1' only after configuring the other bits in this
register.
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Peripheral and Electrical Specifications
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