SM320C6727B-EP Datasheet, PDF (15/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
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SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
Figure 2-5 shows the bit layout of the device-level bridge control register (CFGBRIDGE) and Table 2-7
contains a description of the bits.
31
Reserved
15
1
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 2-5. CFGBRIDGE Register Bit Layout (0x4000 0024)
16
0
CSPRST
R/W, 1
Table 2-7. CFGBRIDGE Register Bit Field Description (0x4000 0024)
BIT NO.
NAME
31:1 Reserved
0
CSPRST
RESET VALUE
N/A
1
READ WRITE
N/A
R/W
DESCRIPTION
Reads are indeterminate. Only 0s should be written to these bits.
Resets the CSP Bridge (BR2 in Figure 2-4).
1 = Bridge Reset Asserted
0 = Bridge Reset Released
CAUTION
The CSPRST bit must be asserted after any change to the PLL that affects SYSCLK1
and SYSCLK2 and must be released before any accesses to the CSP bridge occur from
either the dMAX or the UHPI.
Copyright © 2011, Texas Instruments Incorporated
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