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SM320C6727B-EP Datasheet, PDF (23/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor
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SIGNAL NAME
UHPI_HD[0]
UHPI_HD[1]
UHPI_HD[2]
UHPI_HD[3]
UHPI_HD[4]
UHPI_HD[5]
UHPI_HD[6]
UHPI_HD[7]
UHPI_HD[8]
UHPI_HD[9]
UHPI_HD[10]
UHPI_HD[11]
UHPI_HD[12]
UHPI_HD[13]
UHPI_HD[14]
UHPI_HD[15]
UHPI_HD[16]/HHWIL
UHPI_HD[17]
UHPI_HD[18]
UHPI_HD[19]
UHPI_HD[20]
UHPI_HD[21]
UHPI_HD[22]
UHPI_HD[23]
UHPI_HD[24]
UHPI_HD[25]
UHPI_HD[26]
UHPI_HD[27]
UHPI_HD[28]
UHPI_HD[29]
UHPI_HD[30]
UHPI_HD[31]
UHPI_HBE[0]
UHPI_HBE[1]
UHPI_HBE[2]
UHPI_HBE[3]
UHPI_HCNTL[0]
UHPI_HCNTL[1]
UHPI_HAS
UHPI_HRW
UHPI_HDS[1]
UHPI_HDS[2]
UHPI_HCS
UHPI_HRDY
SM320C6727B-EP
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
Table 2-12. Terminal Functions (continued)
PIN
TYPE(1) PULL(2) GPIO(3)
DESCRIPTION
Universal Host-Port Interface (UHPI) Data and Control
K13
IO
IPD
Y
K14
IO
IPD
Y
M14
IO
IPD
Y
L13
IO
IPD
Y
L14
IO
IPD
Y
N13
IO
IPD
Y
N14
IO
IPD
Y
P14
IO
IPD
E14
IO
IPD
Y
UHPI Data Bus [Lower 16 Bits]
Y
F14
IO
IPD
Y
F13
IO
IPD
Y
G14
IO
IPD
Y
G13
IO
IPD
Y
H14
IO
IPD
Y
H13
IO
IPD
Y
J13
IO
IPD
Y
H1
IO/I
IPD
Y
G3
IO
IPD
Y
G4
IO
IPD
Y
F3
IO
IPD
Y
F4
IO
IPD
E3
IO
IPD
D3
IO
IPD
C3
IO
IPD
P2
IO
IPD
N2
IO
IPD
N3
IO
IPD
M3
IO
IPD
Y
UHPI Data Bus [Upper 16 Bits (IO)] in the following modes:
Y
• Fullword Multiplexed Address and Data
Y
• Fullword Non-Multiplexed
Y
UHPI_HHWIL (I) on pin UHPI_HD[16]/HHWIL and GPIO on
Y
other pins in the following mode:
Y
• Half-word Multiplexed Address and Data
Y
In this mode, UHPI_HHWIL indicates whether the high or
Y
low half-word is being addressed.
L3
IO
IPD
Y
L4
IO
IPD
Y
L2
IO
IPD
Y
H4
IO
IPD
Y
Universal Host-Port Interface (UHPI) Control
C6
I
IPD
Y
UHPI Byte Enable for UHPI_HD[7:0]
C5
I
IPD
Y
UHPI Byte Enable for UHPI_HD[15:8]
C4
I
IPD
Y
UHPI Byte Enable for UHPI_HD[23:16]
B2
I
IPD
Y
UHPI Byte Enable for UHPI_HD[31:24]
D9
I
C10
I
IPD
Y
UHPI Control Inputs Select Access Mode
IPD
Y
C9
I
IPD
Y
UHPI Host Address Strobe for Hosts with Multiplexed
Address/Data bus
D8
I
IPD
Y
UHPI Read/not Write Input
D7
I
C7
I
C8
I
IPU
Y
UHPI Select Signals which create the internal HSTROBE
IPU
Y
active when:
IPU
Y
(UHPI_HCS == '0') & (UHPI_HDS[1] != UHPI_HDS[2])
D6
O
IPD
Y
UHPI Ready Output
Copyright © 2011, Texas Instruments Incorporated
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