SM320C6727B-EP Datasheet, PDF (37/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
www.ti.com
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
4.8 Reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The
RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core
and I/O voltages have reached their proper operating conditions. As a best practice, RESET should be
held low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages
should be at their proper operating conditions.
4.8.1 Reset Electrical Data/Timing
Table 4-1 assumes testing over recommended operating conditions.
NO.
1
2
3
t_w(RSTL)
t_su(BPV-RSTH)
t_h(RSTH-BPV)
Table 4-1. Reset Timing Requirements
Pulse width, RESET low
Setup time, boot pins valid before RESET high
Hold time, boot pins valid after RESET high
MIN
MAX UNIT
100
ns
20
ns
20
ns
Copyright © 2011, Texas Instruments Incorporated
Peripheral and Electrical Specifications
37
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