SM320C6727B-EP Datasheet, PDF (13/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
www.ti.com
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
2.6 High-Performance Crossbar Switch
The C672x DSP includes a high-performance crossbar switch that acts as a central hub between bus
masters and targets. Figure 2-4 illustrates the connectivity of the crossbar switch.
ROM
RAM
CPU
Program
Cache
Memory Controller
Data
Master
Port
(DMP)
CPU
Slave
Port
(CSP)
Program
Master
Port
(PMP)
M1
T1
M2
EMIF
T2
External
Memory
SDRAM/
Flash
Priority
2
1
BR1
BR2
SYSCLK1
SYSCLK1
SYSCLK2
SYSCLK2
BR3
BR4
SYSCLK3
SYSCLK3
SYSCLK1
SYSCLK2
PLL RTI SPI0 SPI1 I2C0 I2C1
Peripheral Configuration Bus
T3
McASP0 McASP1 McASP2
McASP DMA Bus
T4
Priority
1
2
3
Priority
1
2
3
4
Priority
1
2
3
Priority
1
2
dMAX MAX0 Unit Master Port − High Priority
dMAX MAX1 Unit Master Port − Second Priority
Memory Controller DMP − Data Read/Write by CPU
Crossbar
UHPI Master Interface (External Host CPU)
External
Host MCU
M5
UHPI
Config
Universal Host-Port
Interface
1
2
3
Priority
M3
M4
MAX0 MAX1
dMAX
T5
Config
Figure 2-4. Block Diagram of Crossbar Switch
As shown in Figure 2-4, there are five bus masters:
M1
Memory controller DMP for CPU data accesses to peripherals and EMIF.
M2
Memory controller PMP for program cache fills from the EMIF.
M3
dMAX HiMAX master port for high-priority DMA accesses.
M4
dMAX LoMAX master port for lower-priority DMA accesses.
M5
UHPI master port for an external MCU to access on-chip and off-chip memories.
Copyright © 2011, Texas Instruments Incorporated
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