SM320C6727B-EP Datasheet, PDF (86/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
Table 4-30. Additional⁽¹⁾ SPI Slave Timings, 4-Pin Enable Option^{(2) (3)}
NO.
Delay from final
24 t_{d(SPC_ENAH)S} SPIx_CLK edge to slave
deasserting SPIx_ENA.
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
MIN
P – 10
0.5t_c(SPC)M + P – 10
P – 10
0.5t_c(SPC)M + P – 10
MAX UNIT
3P + 15
0.5t_c(SPC)M + 3P + 15
ns
3P + 15
0.5t_c(SPC)M + 3P + 15
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-26).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 4-31. Additional⁽¹⁾ SPI Slave Timings, 4-Pin Chip Select Option^{(2) (3)}
NO.
25 t_{d(SCSL_SPC)S}
Required delay from SPIx_SCS asserted at slave to first
SPIx_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPIx_CLK falling
26 t_{d(SPC_SCSH)S}
Required delay from final
SPIx_CLK edge before
SPIx_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
27
t_{ena(SCSL_SOMI)S}
Delay from master asserting SPIx_SCS to slave driving
SPIx_SOMI valid
28
t_{dis(SCSH_SOMI)S}
Delay from master deasserting SPIx_SCS to slave 3-stating
SPIx_SOMI
MIN
P
0.5t_c(SPC)M + P + 10
P + 10
0.5t_c(SPC)M + P + 10
P + 10
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-26).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
MAX UNIT
ns
ns
P + 15 ns
P + 15 ns
86
Peripheral and Electrical Specifications
Copyright © 2011, Texas Instruments Incorporated
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