SM320C6727B-EP Datasheet, PDF (67/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
www.ti.com
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
4.13 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
• Flexible clock and frame sync generation logic and on-chip dividers
• Up to sixteen transmit or receive data pins and serializers
• Large number of serial data format options, including:
– TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst).
– Time slots of 8,12,16, 20, 24, 28, and 32 bits.
– First bit delay 0, 1, or 2 clocks.
– MSB or LSB first bit order.
– Left- or right-aligned data words within time slots
• DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers.
• Extensive error-checking and mute generation logic
• All unused pins GPIO-capable
Peripheral
Configuration
Bus
McASP
DMA Bus
(Dedicated)
GIO
Control
DIT RAM
384 C
384 U
Optional
Transmit
Formatter
Receive Logic
Clock/Frame Generator
State Machine
Clock Check and
Error Detection
Transmit Logic
Clock/Frame Generator
State Machine
Serializer 0
Serializer 1
Pins
Function
AHCLKRx Receive Master Clock
ACLKRx Receive Bit Clock
AFSRx Receive Left/Right Clock or Frame Sync
AMUTEINx
AMUTEx
The McASPs DO NOT have
dedicated AMUTEINx pins.
AFSXx
Transmit Left/Right Clock or Frame Sync
ACLKXx Transmit Bit Clock
AHCLKXx Transmit Master Clock
AXRx[0] Transmit/Receive Serial Data Pin
AXRx[1] Transmit/Receive Serial Data Pin
Receive
Formatter
Serializer y
McASPx (x = 0, 1, 2)
AXRx[y] Transmit/Receive Serial Data Pin
Figure 4-27. McASP Block Diagram
Copyright © 2011, Texas Instruments Incorporated
Peripheral and Electrical Specifications
67
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