SM320C6727B-EP Datasheet, PDF (29/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
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3 Device Configurations
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
3.1 Device Configuration Registers
The C672x DSP includes several device-level configuration registers, which are listed in Table 3-1. These
registers need to be programmed as part of the device initialization procedure. See Section 3.2.
Table 3-1. Device-Level Configuration Registers
REGISTER NAME
CFGPIN0
CFGPIN1
CFGHPI
CFGHPIAMSB
BYTE ADDRESS
0x4000 0000
0x4000 0004
0x4000 0008
0x4000 000C
CFGHPIAUMB
0x4000 0010
CFGRTI
0x4000 0014
CFGMCASP0
CFGMCASP1
CFGMCASP2 ⁽¹⁾
CFGBRIDGE
0x4000 0018
0x4000 001C
0x4000 0020
0x4000 0024
(1) CFGMCASP2 is reserved on the C6722.
DESCRIPTION
DEFINED
Captures values of eight pins on rising edge of RESET pin.
Table 2-10
Captures values of eight pins on rising edge of RESET pin.
Table 2-11
Controls enable of UHPI and selection of its operating mode.
Table 4-12
Controls upper byte of UHPI address into C672x address space in
Non-Multiplexed Mode or if explicitly enabled for security purposes.
Table 4-13
Controls upper middle byte of UHPI address into C672x address space Table 4-14
in Non-Multiplexed Mode or if explicitly enabled for security purposes.
Selects the sources for the RTI Input Captures from among the six
McASP DMA events.
Table 4-37
Selects the peripheral pin to be used as AMUTEIN0.
Table 4-19
Selects the peripheral pin to be used as AMUTEIN1.
Table 4-20
Selects the peripheral pin to be used as AMUTEIN2.
Table 4-21
Controls reset of the bridge BR2 in Figure 2-4. This bridge must be reset Table 2-7
explicitly after any change to the PLL controller affecting SYSCLK1 and
SYSCLK2 and before the dMAX or UHPI accesses the CPU Slave Port
(CSP).
3.2 Peripheral Pin Multiplexing Options
This section describes the options for configuring peripherals which share pins on the C672x DSP.
Table 3-2 lists the options for configuring the SPI0, I2C0, and I2C1 peripheral pins.
PERIPHERAL
PINS
Table 3-2. Options for Configuring SPI0, I2C0, and I2C1
SPI0
I2C0
I2C1
SPI0_SOMI/I2C0_SDA
SPI0_SIMO
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
SPI0_ENA/I2C1_SDA
CONFIGURATION
OPTION 1
OPTION 2
OPTION 3
3-, 4,- or 5-pin mode 3-pin mode
disabled
disabled
disabled
enabled
disabled
enabled
enabled
SPI0_SOMI
SPI0_SOMI
I2C0_SDA
SPI0_SIMO
SPI0_SIMO
GPIO through SPI0_SIMO pin control
SPI0_CLK
SPI0_CLK
I2C0_SCL
SPI0_SCS
I2C1_SCL
I2C1_SCL
SPI0_ENA
I2C1_SDA
I2C1_SDA
Copyright © 2011, Texas Instruments Incorporated
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Device Configurations
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