SM320C6727B-EP Datasheet, PDF (63/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
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SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
Table 4-16. UHPI Read and Write Switching Characteristics^{(1) (2)}
NO.
PARAMETER
MIN
MAX UNIT
Case 1. HPIC or HPIA read
1
15
Case 2. HPID read with no
auto-increment
9 * 2H + 20⁽³⁾
1 t_d(DSL-HDV)
Delay time, DS low to HD valid
Case 3. HPID read with
auto-increment and read FIFO
initially empty
9 * 2H + 20⁽³⁾
ns
Case 4. HPID read with
auto-increment and data previously
1
15
prefetched into the read FIFO
2 t_dis(DSH-HDV)
3 t_en(DSL-HDD)
4 t_d(DSL-HRDYH)
5 t_d(DSH-HRDYH)
6 t_d(DSL-HRDYL)
Disable time, HD high-impedance from DS high
Enable time, HD driven from DS low
Delay time, DS low to UHPI_HRDY high
Delay time, DS high to UHPI_HRDY high
Delay time, DS low to UHPI_HRDY
low
Case 1. HPID read with no
auto-increment
Case 2. HPID read with
auto-increment and read FIFO
initialy empty
1
4 ns
3
15 ns
12 ns
12 ns
10 * 2H + 20⁽³⁾
ns
10 * 2H + 20⁽³⁾
7 t_d(HDV-HRDYL)
34 t_d(DSH-HRDYL)
Delay time, HD valid to UHPI_HRDY low
Delay time, DS high to
UHPI_HRDY low
Case 1. HPIA write
Case 2. HPID read with
auto-increment and read FIFO
initially empty
0
ns
5 * 2H + 20⁽³⁾
5 * 2H + 20⁽³⁾
ns
35 t_d(DSL-HRDYL)
Delay time, DS low to UHPI_HRDY low for HPIA write and FIFO not
empty
40 * 2H + 20⁽³⁾
ns
36 t_{d(HASL-HRDYH)}
Delay time, UHPI_HAS low to UHPI_HRDY high
12 ns
(1) H = 0.5 * SYSCLK2 period
(2) DS refers to HSTROBE. HAD refers to UHPI_HCNTL[0], UHPI_HCNTL[1], UHPI_HHWIL, and UHPI_HRW.
(3) Max delay is a best case, assuming no delays due to resource conflicts between UHPI and dMAX or CPU. UHPI_HRDY should always
be used to indicate when an access is complete instead of relying on these parameters.
Copyright © 2011, Texas Instruments Incorporated
Peripheral and Electrical Specifications
63
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