SM320C6727B-EP Datasheet, PDF (18/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
Figure 2-6 shows the bit layout of the CFGPIN0 register and Table 2-10 contains a description of the bits.
31
Reserved
7
PINCAP7
6
PINCAP6
5
PINCAP5
4
PINCAP4
3
PINCAP3
2
PINCAP2
1
PINCAP1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 2-6. CFGPIN0 Register Bit Layout (0x4000 0000)
8
0
PINCAP0
Table 2-10. CFGPIN0 Register Bit Field Description (0x4000 0000)
BIT NO.
31:8
7
6
5
4
3
2
1
0
NAME
Reserved
PINCAP7
PINCAP6
PINCAP5
PINCAP4
PINCAP3
PINCAP2
PINCAP1
PINCAP0
DESCRIPTION
Reads are indeterminate. Only 0s should be written to these bits.
SPI0_SOMI/I2C0_SDA pin state captured on rising edge of RESET pin.
SPI0_SIMO pin state captured on rising edge of RESET pin.
SPI0_CLK/I2C0_SCL pin state captured on rising edge of RESET pin.
SPI0_SCS/I2C1_SCL pin state captured on rising edge of RESET pin.
SPI0_ENA/I2C1_SDA pin state captured on rising edge of RESET pin.
AXR0[8]/AXR1[5]/SPI1_SOMI pin state captured on rising edge of RESET pin.
AXR0[9]/AXR1[4]/SPI1_SIMO pin state captured on rising edge of RESET pin.
AXR0[7]/SPI1_CLK pin state captured on rising edge of RESET pin.
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