SM320C6727B-EP Datasheet, PDF (48/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
4.11.3 EMIF Electrical Data/Timing
Table 4-5 through Table 4-8 assume testing over recommended operating conditions (see Figure 4-9
through Figure 4-15).
NO.
19
20
t_{su(EM_DV-EM_CLKH)}
t_{h(EM_CLKH-EM_DIV)}
Table 4-5. EMIF SDRAM Interface Timing Requirements
Input setup time, read data valid on D[31:0] before EM_CLK rising
Input hold time, read data valid on D[31:0] after EM_CLK rising
MIN
MAX UNIT
3
ns
1.9
ns
Table 4-6. EMIF SDRAM Interface Switching Characteristics
NO.
1
2
3
4
5
6
7
t_{c(EM_CLK)}
t_{w(EM_CLK)}
t_{d(EM_CLKH-EM_CSV)S}
t_{oh(EM_CLKH-EM_CSIV)S}
t_{d(EM_CLKH-EM_WE-DQMV)S}
t_{oh(EM_CLKH-EM_WE-DQMIV)S}
t_{d(EM_CLKH-EM_AV)S}
8
t_{oh(EM_CLKH-EM_AIV)S}
9
t_{d(EM_CLKH-EM_DV)S}
10 t_{oh(EM_CLKH-EM_DIV)S}
11 t_{d(EM_CLKH-EM_RASV)S}
12 t_{oh(EM_CLKH-EM_RASIV)S}
13 t_{d(EM_CLKH-EM_CASV)S}
14 t_{oh(EM_CLKH-EM_CASIV)S}
15 t_{d(EM_CLKH-EM_WEV)S}
16 t_{oh(EM_CLKH-EM_WEIV)S}
17 t_{dis(EM_CLKH-EM_DHZ)S}
18 t_{ena(EM_CLKH-EM_DLZ)S}
PARAMETER
Cycle time, EMIF clock EM_CLK
Pulse width, EMIF clock EM_CLK high or low
Delay time, EM_CLK rising to EM_CS[0] valid
Output hold time, EM_CLK rising to EM_CS[0] invalid
Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid
Output hold time, EM_CLK rising to EM_WE_DQM[3:0] invalid
Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid
Output hold time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0]
invalid
Delay time, EM_CLK rising to EM_D[31:0] valid
Output hold time, EM_CLK rising to EM_D[31:0] invalid
Delay time, EM_CLK rising to EM_RAS valid
Output hold time, EM_CLK rising to EM_RAS invalid
Delay time, EM_CLK rising to EM_CAS valid
Output hold time, EM_CLK rising to EM_CAS invalid
Delay time, EM_CLK rising to EM_WE valid
Output hold time, EM_CLK rising to EM_WE invalid
Delay time, EM_CLK rising to EM_D[31:0] 3-stated
Output hold time, EM_CLK rising to EM_D[31:0] driving
MIN
10
3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
MAX UNIT
ns
ns
7.7 ns
ns
7.7 ns
ns
7.7 ns
ns
7.7 ns
ns
7.7 ns
ns
7.7 ns
ns
7.7 ns
ns
7.7 ns
ns
48
Peripheral and Electrical Specifications
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