SM320C6727B-EP Datasheet, PDF (61/109 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SM320C6727B-EP
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SPRS793A – SEPTEMBER 2011 – REVISED OCTOBER 2011
31
8
Reserved
7
0
HPIAMSB
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-21. CFGHPIAMSB Register Bit Layout (0x4000 000C)
Table 4-13. CFGHPIAMSB Register Bit Field Description (0x4000 000C)
BIT NO.
NAME
31:8 Reserved
7:0 HPIAMSB
RESET
VALUE
N/A
0
READ
WRITE
N/A
R/W
DESCRIPTION
Reads are indeterminate. Only 0s should be written to these bits.
UHPI most significant byte of DSP address to access in Non-Multiplexed mode and
in Multiplexed Address and Data mode when PAGEM = 1. Sets bits [31:24] of the
DSP internal address as accessed through UHPI.
31
8
Reserved
7
0
HPIAUMB
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-22. CFGHPIAUMB Register Bit Layout (0x4000 0010)
Table 4-14. CFGHPIAUMB Register Bit Field Description (0x4000 0010)
BIT NO.
NAME
31:8 Reserved
7:0 HPIAUMB
RESET
VALUE
N/A
0
READ
WRITE
N/A
R/W
DESCRIPTION
Reads are indeterminate. Only 0s should be written to these bits.
UHPI upper middle byte of DSP address to access in Non-Multiplexed mode and in
Multiplexed Address and Data mode when PAGEM = 1. Sets bits [23:16] of the DSP
internal address as accessed through UHPI.
Copyright © 2011, Texas Instruments Incorporated
Peripheral and Electrical Specifications
61
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