THS3217 Datasheet, PDF (8/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
www.ti.com
Electrical Characteristics: OPS (continued)
at +V_CC = 6.0 V, –V_CC = –6.0 V, 25-Ω D2S source impedance, D2S input common-mode voltage (V_IC) = 0.25 V, V_REF = GND,
R_F = 249 Ω⁽¹⁾, R_G = 162 Ω, A_V = 2.5 V/V, OPS R_LOAD = 100 Ω, OPS enabled (DISABLE ≤ 0.7 V or floated), external OPS input
selected (PATHSEL ≥ 1.3 V), and T_J ≈ 25˚C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TEST
MIN
TYP
MAX UNIT LEVEL
(2)
Input headroom to either supply
Common-mode rejection ratio
(CMRR)
T_J = 25°C
Noninverting input resistance
Noninverting input capacitance
Open-loop inverting input impedance
OUTPUT ⁽⁶⁾
Output voltage headroom to either
supply
R_LOAD = 500 Ω
Linear output current
Peak output current
DC output impedance
T_J = 25°C, ±2.5 V into 26-Ω R_LOAD
0-V output, R_LOAD < 0.2 Ω
0-V output, load current = ±40 mA
Internal R_F
PATHSEL (Pin 4; Logic Reference = Pin 7 = GND)
Input low logic level
Internal path selected
Input high logic level
External input selected at VIN (pin 9)
Input voltage range
PATHSEL voltage when floated
Internal input from D2S selected
Input pin bias current⁽⁷⁾
0-V input
3.3-V input
Input pin impedance
Switching time
To 1% of final value
Input switching glitch
Both inputs at GND
Deselected input dc isolation
± 2-V input
Deselected input ac isolation
2 V_PP, at 20-MHz input
DISABLE (Pin 10; Logic Reference = Pin 7 = GND)
Input low logic level
Input high logic level
Shutdown control voltage range
Shutdown voltage when floated
Output stage enabled
Input pin bias current⁽⁷⁾
0-V input
3.3-V input
Input pin impedance
Switching time (turn on or off)
To 10% of final value
Shutdown dc isolation (either input) ±2-V input
Shutdown ac isolation (either input) 2 V_PP at 20-MHz input
POWER SUPPLY
Bipolar-supply operating range
Single-supply operating range
Supply current (OPS only)
±6-V supplies
Disabled supply current in OPS
Logic reference current at pin 7⁽⁷⁾
±6-V supplies
Pins 4, 7, and 10 held at 0 V
2.6
47
49
17.6
18.5
3.3
42
1.1
1.3
95
120
135
170
0.05
17.6
18.5
0.7
–0.5
0
0
–150
70
55
0.9
0.9
20
18 || 1.5
80
50
80
65
0.7
–0.5
0
0
–150
70
55
0.9
0.9
20
18 || 1.5
200
80
65
±4.0
±6.0
8
12
18.5
21
2.0
2.4
200
280
3.0
V
A
dB
A
22.4
kΩ
A
pF
C
Ω
C
1.4
V
A
mA
A
mA
A
0.10
Ω
A
22.4
kΩ
A
V
A
1.3
V
A
+V_CC
V
A
40 mV
A
4
µA
A
–250
µA
A
kΩ || pF
C
ns
C
mV
C
dB
A
dB
C
V
A
1.3
V
A
+V_CC
V
B
40 mV
A
4
µA
A
–250
µA
A
kΩ || pF
C
ns
C
dB
A
dB
C
±7.9
V
A
15.8
V
B
24.5 mA
A
3.0 mA
C
380
µA
A
(6) Output measured at pin 11.
(7) Currents out of pin treated as a positive polarity.
8
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