THS3217 Datasheet, PDF (41/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
Using the PS to receive and amplify a signal in the inverting mode with a matched terminating impedance,
requires another resistor to ground (R_M) along with R_G. This R_M resistor is shown in Figure 85 for a 50-Ω
matched input impedance design.
50-Ÿ
Source
VIN-
12
RG
RF
RM
OPS
Stage
6
From D2S
VIN+ 9
11 VOUT
+
Figure 85. Inverting OPS Operation With Matched Input Impedance
Table 4 gives the recommended external resistor values versus gain for the inverting gain mode with input
matching configuration. Table 4 solves for the required R_F to simultaneously allow the gain, input impedance (50
Ω), and feedback transimpedance to be controlled to the optimum target values. The table includes the effect of
the internal 18.5-kΩ feedback resistor, and minimizes the RMS error to input impedance target (Z_I) and overall
gain.
TARGET
GAIN
(V/V)
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
Table 4. Resistor Values Versus Gain for the Inverting OPS Configuration
MEASURED
SSBW
(MHz)
1000
—
—
860
—
—
—
—
760
—
—
—
—
—
—
—
—
—
260
BEST BEST BEST
R_F (Ω) R_G (Ω) R_M (Ω)
280
274
60.4
255
169
71.5
249
124
84.5
237 93.1 107
226
75
150
226 63.4 237
221 54.9 604
226 49.9 Open
249 49.9 Open
274 49.9 Open
301 49.9 Open
324 49.9 Open
348 49.9 Open
374 49.9 Open
402 49.9 Open
422 49.9 Open
449 49.9 Open
475 49.9 Open
499 49.9 Open
CALCULATED GAIN
(V/V)
(dB)
1.002
1.506
2.000
2.490
3.013
3.491
4.010
4.525
4.985
5.485
6.026
6.486
6.967
7.487
8.048
8.448
8.989
9.509
9.990
0.022
3.554
6.019
7.924
9.581
10.859
12.064
13.111
13.953
14.784
15.601
16.240
16.861
17.487
18.114
18.536
19.074
19.563
19.991
GAIN ERROR
(%)
0.250
0.376
–0.014
–0.403
0.444
–0.258
0.259
0.545
–0.301
–0.264
0.434
–0.208
–0.472
–0.167
0.600
–0.607
–0.123
0.100
–0.100
Z_I (Ω)
49.490
50.243
50.254
49.784
50.000
50.019
50.326
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
Z_I ERROR
(%)
–1.019
0.486
0.508
–0.433
0.000
0.039
0.651
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
At higher gains, R_M increases to larger values, and the resistor is excluded from the circuit. The resulting input
impedance of the network is resistor R_G. From that point, R_F simply increases to get higher gains, thereby rapidly
reducing the SSBW. However, below a gain of –5 V/V, the inverting design with the values shown in Table 4
holds a more constant SSBW versus the noninverting mode (see Figure 26).
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