THS3217 Datasheet, PDF (29/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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9 Detailed Description
THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
9.1 Overview
The THS3217 is a differential-input to single-ended output amplifier system that provides the necessary
functional blocks to convert a differential output signal from a wideband DAC to a dc-coupled, single-ended, high-
power output signal. The THS3217 typically operates using balanced, split supplies. Signal swings through the
device can be adjusted around ground at several points within the device. Single-supply operation is also
supported an ac-coupled signal path. The THS3217 supply voltage ranges from ±4.0 V to ±7.9 V. The two
internal logic gates rely on a logic reference voltage at pin 7 that is usually tied to ground for any combination of
power-supply voltages. The DISABLE control (pin 10) turns the output power stage (OPS) off to reduce power
consumption when not in use.
A differential-to-single-ended stage (D2S) provides a high input impedance for a high-speed DAC (plus any
reconstruction filter between the DAC and THS3217) operating over a common-mode input voltage range from
–1 V to +3.0 V. This range is intended to support either current sourcing or current sinking DACs. The D2S is
internally configured to reject the input common-mode voltage and convert the differential inputs to a single-
ended output at a fixed gain of 2 V/V (6 dB).
An uncommitted, on-chip, wideband, unity-gain buffer is provided (between pins 1 and 15) to drive the VREF pin.
The buffer offers extremely broad bandwidth to achieve very-low output impedance to high frequencies
(Figure 51). The buffer does not provide a high full-power bandwidth because of a relatively low slew rate. The
buffer stage includes a default midsupply bias resistor string of 50-kΩ each to set the default input to midsupply.
This 25-kΩ Thevinin impedance is easily overridden with an external input source, but is intended to provide a
midsupply bias for single-supply operation. The buffer amplifier that drives the VREF pin has two functions:
• Provides an easy-to-interface, dc-correction, servo-loop input
• Can be used as an offset injection point for the D2S output
The final OPS provides one of the highest-performance, current-feedback amplifiers available for line-driving
applications. The 950-MHz SSBW stage provides 5000 V/μs of slew-rate, sufficient to drive a 5-V_PP output with
500-MHz bandwidth. In addition, the OPS is able to drive a very-high continuous and peak output current
sufficient to drive the most demanding loads at very high speeds. A unique feature added to the OPS is a 2 × 1
input multiplexer at the noninverting input. The PATHSEL control (pin 4) is used to select the appropriate signal
path to the OPS noninverting input. One of the multiplexer select paths passes the internal D2S output directly to
the OPS. The other select path accepts an external input to the OPS at VIN+ (pin 9). This configuration allows
the D2S output, available at VO1 (pin 6), to pass through an external RLC filter and back into the OPS at VIN+
(pin 9).
If the OPS does not require power for certain application configurations, a shutdown feature has been included to
reduce power consumption. For designs that do not use the OPS at all, two internal fixed resistors are included
to define the operating points for the disabled OPS. An approximate 18.5-kΩ resistor to the logic reference (pin
7) from VIN+ (pin 9), and an approximate 18.5-kΩ, fixed, internal feedback resistor are included to hold the OPS
pin voltages in range if no external resistors are used around the OPS. These resistors must be included in the
design calculations for any external network.
Two sets of power supply-pins have been provided for both the positive and negative supplies. Pin 5 (–VCC2)
and pin 16 (+VCC2) power the D2S and midscale buffer stages, while pin 8 (–VCC1) and pin 13 (+VCC1) supply
power to the OPS. The supply rails are connected internally by antiparallel diodes. Externally, connect power first
to the OPS, then connect back on each side with a π-filter (ferrite bead + capacitor) to the input-stage supply
pins (see Figure 90). Do not use mismatched supply voltages on either the positive or negative sides because
the supplies are internally connected through the antiparallel diodes. Imbalanced positive and negative supplies
are acceptable, however.
When the OPS is disabled, the output pin goes to high impedance. However, do not connect two OPS outputs
from different devices together and select them as a wired-or multiplexer. Although the high-impedance output is
disabled, the inverting node is still available through the feedback resistor, and can load the active signal. The
signal path through the inverting node typically degrades the distortion on the desired active signal in a wired-or
multiplexer configuration using CFA amplifiers.
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