THS3217 Datasheet, PDF (35/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
Feature Description (continued)
The buffer provides a very wideband, low output-impedance when used to drive the VREF pin (see Figure 51).
To provide this low broadband impedance, the closed-loop midscale (dc) reference buffer offers a very
broadband SSBW, but only a modest large-signal bandwidth (LSBW); see Figure 49. This path is not normally
intended to inject a wideband signal, but can be used for lower-amplitude signals. Driving the buffer output into
the VREF pin allows a wideband small-signal term to be added into the D2S along with the signal from the
differential inputs.
The midscale (or dc) reference buffer injects an offset voltage to the output offset of the D2S when it drives the
VREF pin. The offset has very low drift, but consider the effect of the input bias current times the dc source
impedance at VMID_IN (pin 1). When used as a default midsupply reference for single-supply operation, the
input to this buffer is just the average of the total power supplies though a 25-kΩ source impedance. Add an
external capacitor to filter the supply and the 50-kΩ internal resistors. A 1-µF capacitor on pin 1 adds a 6-Hz pole
to the noise sources. If lower noise at lower frequencies is required, implement a midscale divider with external,
lower-valued resistors in parallel with the internal 50-kΩ values.
If the midscale buffer drive the VREF pin, another noise term is added to Equation 9 and Equation 10. The
midscale buffer 4.4-nV/√Hz voltage noise is amplified by 0 dB, and adds (RMS) a negligible impact to the total
D2S output noise. The biggest impact comes when the internal default 50-kΩ dividers are used. Be sure to
decouple pin 1 with at least a 1-µF capacitor in the application to reduce the noise contribution through this path.
Figure 80 is the simulation circuit where the only change is to add or remove the 1-µF capacitor.
+VCC2
16
50 k
VMID_IN
1
1 …F
50 k
x1
15 VMID_OUT
5
-VCC2
Figure 80. Midscale Buffer Noise Model
Figure 81 shows the simulated output noise for the midscale buffer using the internal 50-kΩ divider with and
without a 1-µF capacitor on pin 1.
1000
With 1PF cap.
Without 1PF cap
100
10
1
1
10
100
1k
10k
100k
1M
Frequency (Hz)
D501
Figure 81. Buffer-Output Noise Comparison With and Without the 1-µF Bypass Capacitor on Pin 1
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