THS3217 Datasheet, PDF (56/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
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10.1.1.2.2 Detailed Design Procedure
Figure 100 shows an example design using the THS3217 to deliver a 10-V_PP maximum voltage from a DAC
input, and includes an example external, third-order, interstage Bessel filter. Some of the salient considerations
for this design include:
1. Reduced DAC output current with increased termination. This example is intended to be used with a current-
sourcing DAC with an output compliance voltage of at least 1 V on a 0.5-V common-mode voltage. The 10-
mA, single-ended, DAC tail current produces a 0-V to 1-V swing on each 100-Ω termination. The resulting 2-
V_PP differential DAC signal produces a higher SNR signal at the THS3217 inputs.
2. The midscale buffer is not used. The VREF pin is grounded to set the inputs to a 4-V_PP ground-centered
maximum output swing at VO1 (pin 6). The external input to the OPS is selected by setting PATHSEL to 3.3
V (anything over 1.3 V is adequate, or tie this pin to +V_CC for fixed, external-path operation).
3. The interstage Bessel filter is –0.3-dB flat through 20 MHz, with only 1.6 dB of insertion loss. The filter is
designed to be low insertion-loss with relatively high resistor values. The filter uses standard inductor values.
The capacitors are also standard-value, and slightly off from the exact filter solution. The final resistor to
ground is designed for 500 Ω, but increased here to a standard 511 Ω externally to account for the internal
18.5-kΩ resistor on the external OPS input pin to GND. To isolate the last 47-pF filter capacitor from the OPS
input stage, a 10-Ω series resistor is added close to the pin 9 input.
4. The filter adds 1.6 dB of insertion loss that is recovered, to achieve a 10-V_PP maximum output by designing
the OPS for a gain of 3 V/V. Looking at Table 7, this gain setting requires the 232-Ω external R_F and 113-Ω
R_G to ground for best operation.
5. For 10-V_PP maximum output, using the ±7.5-V supplies shown here gives adequate headroom in the OPS
output stage. The operating maximum supply of 15.8 V requires a 5% tolerance on these ±7.5-V supplies.
6. The Bessel filter gives a very low overshoot full-scale output step-response, as shown in the 10-MHz, ±5-V
square wave of Figure 102. The frequency response of the system is shown in Figure 101.
10.1.1.2.3 Application Curves
16
14
12
10
8
6
4
1M
10M
Frequency (Hz)
6
10 V_PP
4
2
0
-2
-4
-6
100M
D511
r5 V
Time (25ns/div)
D512
Figure 101. Frequency Response of the System With the
Interstage Bessel Filter
Figure 102. Pulse Response of the System With the
Interstage Bessel Filter
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