THS3217 Datasheet, PDF (2/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics: D2S.................................. 5
7.6 Electrical Characteristics: OPS ................................. 7
7.7 Electrical Characteristics: D2S + OPS...................... 9
7.8 Electrical Characteristics: Midscale (DC) Reference
Buffer........................................................................ 10
7.9 Typical Characteristics: D2S + OPS ....................... 11
7.10 Typical Characteristics: D2S Only ........................ 13
7.11 Typical Characteristics: OPS only......................... 15
7.12 Typical Characteristics: Midscale (DC) Reference
Buffer........................................................................ 19
7.13 Typical Characteristics: Switching Performance... 20
7.14 Typical Characteristics: Miscellaneous Performance
................................................................................. 21
8 Parameter Measurement Information ................ 22
8.1 Overview ................................................................. 22
8.2 Frequency Response Measurement ....................... 23
8.3 Harmonic Distortion Measurement ......................... 24
8.4 Noise Measurement ................................................ 25
8.5 Output Impedance Measurement ........................... 25
8.6 Step-Response Measurement ................................ 25
8.7 Feedthrough Measurement..................................... 26
8.8 Midscale Buffer R_OUT Versus C_LOAD Measurement 28
9 Detailed Description ............................................ 29
9.1 Overview ................................................................. 29
9.2 Functional Block Diagram ....................................... 30
9.3 Feature Description................................................. 30
9.4 Device Functional Modes........................................ 46
10 Application and Implementation........................ 52
10.1 Application Information.......................................... 52
11 Power Supply Recommendations ..................... 61
11.1 Thermal Considerations ........................................ 62
12 Layout................................................................... 63
12.1 Layout Guidelines ................................................. 63
12.2 Layout Example .................................................... 64
13 Device and Documentation Support ................. 65
13.1 Device Support...................................................... 65
13.2 Documentation Support ........................................ 65
13.3 Community Resources.......................................... 65
13.4 Trademarks ........................................................... 66
13.5 Electrostatic Discharge Caution ............................ 66
13.6 Glossary ................................................................ 66
14 Mechanical, Packaging, and Orderable
Information ........................................................... 66
4 Revision History
Changes from Revision A (February 2016) to Revision B
Page
• Deleted open-loop transimpedance gain max value .............................................................................................................. 7
• Deleted external to internal input offset voltage match min and max values ......................................................................... 7
• Changed external to internal input offset voltage match test level from A to C .................................................................... 7
• Deleted dc output impedance min and max values ............................................................................................................. 10
• Changed dc output impedance test level from A to C.......................................................................................................... 10
Changes from Original (February 2016) to Revision A
Page
• Changed from product preview to production data ................................................................................................................ 1
2
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