THS3217 Datasheet, PDF (43/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
The OPS includes a disable feature that reduces power consumption from approximately 21 mA to 2.4 mA. The
logic controls are intended to be ground-referenced regardless of the power supplies used. The logic reference
(GND, pin 7) is normally grounded and also provides a connection to the internal 18.5-kΩ resistor on pin 9
(default bias to pin 7). Operating in a single-supply configuration with –V_CC at GND and the external OPS input
(pin 9) floated, places pin 9 internally at –V_CC = GND. Driving the external OPS input (pin 9) from a source within
the operating range overrides the bias to –V_CC. However, if the application requires pin 9 to be floated in a
single-supply operation, consider centering the voltage on pin 9 with an added 18.5-kΩ external resistor to the
+V_CC supply.
If the disable feature is not needed, simply float or ground DISABLE (pin 10) to hold the OPS in the enabled
state. Increasing the voltage on the DISABLE pin greater than 1.3 V disables the OPS and reduces the current to
approximately 2.4 mA. If the OPS is unused in the application, it can be disabled by tying pin 10 to +V_CC, even
up to the maximum operating supply of 15.8 V in a single-supply design.
Do not move the logic threshold away from those set by the logic ground at pin 7. If a different logic swing level
is required, and pin 7 is biased to a different voltage, be sure the source can sink the typical 280 µA coming out
of pin 7. Also recognize that the 18.5-kΩ bias resistor on the external OPS input (pin 9) is connected to pin 7
voltage internally.
As shown in Figure 56, the OPS enables in approximately 100 ns from the logic threshold at 1.0 V while
disabling to a final value in approximately 500 ns.
9.3.3.2 OPS Harmonic Distortion (HD) Performance
The OPS in the THS3217 provides one of the best HD solutions available through high power levels and
frequencies. Figure 31 and Figure 32 show the swept-frequency HD2 and HD3, where the second harmonic is
clearly the dominant term over the third harmonic. Typical wideband CFA distortion is reported only through 2-
V_PP output while Figure 31 and Figure 32 provide sweeps at 5 V_PP and 8 V_PP into a 100-Ω load. These curves
normally show a 20-dB per decade rise with frequency due to loop-gain roll-off. At the highest 8-V_PP swing, the
onset of slew rate limited HD is seen at approximately 40 MHz. The required output signal slew rate at 8 V_PP and
40 MHz is 4 V_PEAK × 2π × 40 MHz = 1000 V/µs. The output signal requires 1/5 of the available slew rate that will
take the HD2 off the 20-dB per decade rate in the –50-dBc operating region shown. A slight shift in the HD3
slope is also seen around 40 MHz for 8-V_PP output in Figure 32.
The distortion performance is extremely robust as a function of R_LOAD (see Figure 33 and Figure 34). Normally,
heavier loads degrade the distortion performance, as seen for the HD3 in Figure 34. However, the HD2 actually
improves slightly going from a 200-Ω load to a 100-Ω load.
One of the key advantages offered by the CFA design in the OPS is that the distortion performance holds
approximately constant over gain, as seen in the full-path distortion measurements of Figure 7 and Figure 8.
Here, the D2S provides a fixed gain of 2 V/V driving a 200-Ω interstage load and using the internal path to drive
the OPS at gains from 1.5 V/V to 10 V/V. Holding the loop-gain approximately constant by adjusting the feedback
R_F value with gain results in vastly improved performance versus a voltage-feedback-based design.
Testing a 5-V_PP output from the OPS with the supplies swept from the minimum ±4 V to ±7.5 V in Figure 35 and
Figure 36 show:
1. The 1.5-V headroom on ±4-V supplies and ±2.5-V output voltage results in degraded performance. At the
lower supplies, target lower output swings for improved linearity performance.
2. The HD2 does not change significantly with supply voltages above ±5 V. The HD3 does improve slightly at
higher supply-voltage settings.
From these plots at ±7.5-V supplies, a 5-V_PP output into 100-Ω load shows better than –60-dBc HD2 and HD3
performance through 50 MHz. This exceptional performance is available with the OPS configured as a
standalone amplifier. Combining this performance with the D2S stage (see Figure 3 and Figure 4) degrades the
distortion due to the D2S and OPS harmonics combining in phase, and internal coupling between the stages.
With the D2S and OPS running together at a final 5-V_PP output and 50 MHz, the HD2 drops to –50 dBc, and HD3
to –58 dBc on ±6-V supplies. Lower output swings for the combined stages provide much lower distortion. The 2-
V_PP output curves on Figure 3 and Figure 4 show –57 dBc for HD2, and a remarkable –76 dBc for HD3 at 50
MHz.
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