THS3217 Datasheet, PDF (5/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
7.5 Electrical Characteristics: D2S
at +V_CC = 6.0 V, –V_CC = –6.0 V, A_V = 2 V/V, 25-Ω source impedance, input common-mode voltage (V_IC) = 0.25 V, external
OPS input selected (PATHSEL ≥ 1.3 V), V_REF = GND, R_LOAD = 100 Ω, and T_J ≈ 25˚C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TEST
MIN
TYP
MAX UNIT LEVEL
(1)
AC PERFORMANCE (Power Stage Disabled: DISABLE pin ≥ 1.3 V) ⁽²⁾
Small-signal bandwidth (SSBW)
Large-signal bandwidth (LSBW)
Bandwidth for 0.2-dB flatness
Slew rate⁽³⁾
Over- and undershoot
Rise and fall time
Settling time to 0.1%
2nd-order harmonic distortion (HD2)
3rd-order harmonic distortion (HD3)
Output voltage noise
V_OUT = 250 mV_PP, peaking < 1.0 dB
V_OUT = 2 V_PP
V_OUT = 2 V_PP
V_OUT = 4-V step
Input t_r = 1 ns, V_OUT = 2-V step
Input t_r = 1 ns, V_OUT = 2-V step
Input t_r = 1 ns, V_OUT = 2-V step
f = 20 MHz, V_OUT= 2 V_PP
f = 20 MHz, V_OUT= 2 V_PP
f > 200 kHz
800
500
250
2500
6%
1.2
5
–68
–86
18
MHz
C
MHz
C
MHz
C
V/µs
C
C
ns
C
ns
C
dBc
C
dBc
C
nV/√Hz
C
Input current noise (each input)
f > 200 kHz
2.0
pA/√Hz
C
Output impedance
DC PERFORMANCE ⁽²⁾
f = 20 MHz
0.8
Ω
C
Differential to single-ended gain
±100-mV output
1.975
2.0
2.025 V/V
A
Differential to single-ended gain drift
VREF input pin gain
VREF input pin gain drift
Output offset voltage
Output offset voltage drift
Input bias current – each input⁽⁴⁾
Input bias current drift
Input offset current
Input offset current drift
INPUTS ⁽⁵⁾
T_J = –40°C to +125°C
Differential inputs = 0 V,
V_REF = ±100 mV
T_J = –40°C to +125°C
T_J = 25°C
T_J = 0°C to 70°C
T_J = –40°C to +125°C
T_J = –40°C to +125°C
T_J = 25°C
T_J = 0°C to 70°C
T_J = –40°C to +125°C
T_J = –40°C to +125°C
T_J = 25°C
T_J = 0°C to 70°C
T_J = –40°C to +125°C
T_J = –40°C to +125°C
0.985
–35
–43
–54
-40
–4
–4.2
–4.3
1
–400
–700
–1180
–12
–20
–24 ppm/°C
B
1.0
1.015 V/V
A
–70
±8
–115
±2
3
±50
±1
–95 ppm/°C
B
35 mV
A
40 mV
B
47 mV
B
–190 µV/°C
B
4
µA
A
4.2
µA
B
4.5
µA
B
5 nA/°C
B
400
nA
A
940
nA
B
1600
nA
B
12 nA/°C
B
Common-mode input negative
supply headroom
Common-mode input positive supply
headroom
Common-mode rejection ratio
(CMRR)
T_J = 25°C
T_J = –40°C to +85°C
T_J = 25°C
T_J = –40°C to +125°C
–1 V ≤ V_IC ≤ 3 V
1.8
1.9
V
A
2.0
V
B
1.3
1.4
V
A
1.5
V
B
47
55
dB
A
Input impedance differential mode
Input impedance common mode
V_CM = 0 V
V_CM = 0 V
50 || 2.4
90 || 2.4
kΩ || pF
C
kΩ || pF
C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈ T_J≈ 25°C; over temperature limits by
characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for
information. DC limits tested with no self-heating. Add internal self heating to T_A for T_J.
(2) Output measured at pin 6.
(3) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π × f_–3dB.
(4) Currents out of pin treated as a positive polarity.
(5) Applies to input pins 2 (IN+) and 3 (IN–).
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