THS3217 Datasheet, PDF (47/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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Device Functional Modes (continued)
Ferrite
Bead
49.9
Differential
V_IN
49.9
16
15
1
50 k
2 x1
50 k
x1
50
+
250
500
3 x1
14
100
4
5
6
7
200
Ferrite
Bead
THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
6V
13
18.5 k
162
12
249
11
AV = 5 V/V
49.9
To
50-Ÿ /RDG
10
18.5 k
9
8
±6 V
Figure 90. Differential to Single-Ended, Gain of 5-V/V Configuration
This configuration shows the test circuit used to generate Figure 1. Some of the key features in this basic
configuration include:
1. The power supplies are brought into the OPS first, then back to the input stage through a π-filter comprised
of a ferrite bead and local decoupling caps on –VCC2 and +VCC2, pins 5 and 16, respectively (see the
Power Supply Recommendations section for more information).
2. The two logic lines are grounded. This logic configuration (with pin 7 grounded) selects the internal path from
the D2S to OPS, and enables the OPS.
3. The external I/O pins of the midscale buffer are left floating.
4. The VREF pin is grounded, thus setting the D2S output common-mode voltage at VO1 (pin 6) to ground.
5. The D2S external output is loaded with a 200-Ω resistor to ground. Lighter loading on the VO1 pin (versus
the 100 Ω used to characterize the D2S only) results in increased frequency response peaking. Heavier
loading degrades the D2S distortion performance.
6. The external OPS input at pin 9 is left floating. However, it is internally tied to ground by the internal 18.5-kΩ
resistor.
7. The feedback resistor in the OPS is set to the parallel combination of the external 249-Ω resistor and the
internal 18.5-kΩ resistor. This 245.7-Ω total R_F with the 162-Ω R_G resistor gives a gain of approximately 2.5
V/V (7.98 dB) in the OPS stage
8. The input D2S gives a gain of 2 V/V (6 dB), and along with the 2.5 V/V (7.98 dB) from the OPS, gives an
overall gain of 5 V/V (13.98 dB) with > 700 MHz of SSBW (see Figure 1).
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